UB Paderborn / Katalog / Suche / in CDI

A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode

IEEE journal of solid-state circuits, 2009-07, Vol.44 (7), p.1907-1913

2009

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Utilizing Process Variations for Reference Generation in a Flash ADC

IEEE transactions on circuits and systems. II, Express briefs, 2009-05, Vol.56 (5), p.364-368

2009

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Jitter Characteristic in Charge Recovery Resonant Clock Distribution

IEEE journal of solid-state circuits, 2007-07, Vol.42 (7), p.1618-1625

2007

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A sub-130-nm conditional keeper technique

IEEE journal of solid-state circuits, 2002-05, Vol.37 (5), p.633-638

2002

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A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization

IEEE journal of solid-state circuits, 2006-10, Vol.41 (10), p.2314-2323

2006

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A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file

IEEE journal of solid-state circuits, 2002-05, Vol.37 (5), p.624-632

2002

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A study of injection locking in ring oscillators

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.5465-5468 Vol. 6

2005

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Studies on Design of Near-Field Wireless-Powered Biphase Implantable Stimulators

Kifle, Yonatan Habteslassie

2022

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A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme

IEEE journal of solid-state circuits, 2003-05, Vol.38 (5), p.755-761

2003

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Least-Squares Phase Predistortion of a +30 dBm Class-D Outphasing RF PA in 65 nm CMOS

IEEE transactions on circuits and systems. I, Regular papers, 2013-07, Vol.60 (7), p.1915-1928

2013

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Design and Analysis of a Class-D Stage With Harmonic Suppression

IEEE transactions on circuits and systems. I, Regular papers, 2012-06, Vol.59 (6), p.1178-1186

2012

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A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13- \mum CMOS for Medical Implant Devices

IEEE journal of solid-state circuits, 2012-07, Vol.47 (7), p.1585-1593

2012

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A 2.4 GS/s, Single-Channel, 31.3 dB SNDR at Nyquist, Pipeline ADC in 65 nm CMOS

IEEE journal of solid-state circuits, 2011-07, Vol.46 (7), p.1575-1584

2011

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Modeling and Digital Predistortion of Class-D Outphasing RF Power Amplifiers

IEEE transactions on microwave theory and techniques, 2012-06, Vol.60 (6), p.1907-1915

2012

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Efficient Integrated Circuits for Wideband Wireless Transceivers

Duong, Quoc-Tai

2016

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Energy-Efficient Data Converters for Low-Power Sensors

Chen, Kairang

2016

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A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s

2012 Proceedings of the ESSCIRC (ESSCIRC), 2012, p.369-372

2012

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A +32 dBm 1.85 GHz class-D outphasing RF PA in 130nm CMOS for WCDMA/LTE

2011 Proceedings of the ESSCIRC (ESSCIRC), 2011, p.127-130

2011

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Phase Predistortion of a Class-D Outphasing RF Amplifier in 90 nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2011-10, Vol.58 (10), p.642-646

2011

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Analysis of a 5.5-V Class-D Stage Used in + 30-dBm Outphasing RF PAs in 130- and 65-nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2012-11, Vol.59 (11), p.726-730

2012

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Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

Zhang, Dai

2014

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Low-Power Delta-Sigma Modulators for Medical Applications

Fazli Yeknami, Ali

2014

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A 3.5GHz 32mW 150nm multiphase clock generator for high-performance microprocessors

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC, 2003, p.112-482 vol.1

2003

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Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

Harikumar, Prakash

2016

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A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for medical implant devices

2011 Proceedings of the ESSCIRC (ESSCIRC), 2011, p.467-470

2011

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A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode

Utilizing Process Variations for Reference Generation in a Flash ADC

Jitter Characteristic in Charge Recovery Resonant Clock Distribution

A sub-130-nm conditional keeper technique

A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization

A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file

A study of injection locking in ring oscillators

Studies on Design of Near-Field Wireless-Powered Biphase Implantable Stimulators

A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme

Least-Squares Phase Predistortion of a +30 dBm Class-D Outphasing RF PA in 65 nm CMOS

Design and Analysis of a Class-D Stage With Harmonic Suppression

A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13- \mum CMOS for Medical Implant Devices

A 2.4 GS/s, Single-Channel, 31.3 dB SNDR at Nyquist, Pipeline ADC in 65 nm CMOS

Modeling and Digital Predistortion of Class-D Outphasing RF Power Amplifiers

Efficient Integrated Circuits for Wideband Wireless Transceivers

Energy-Efficient Data Converters for Low-Power Sensors

A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s

A +32 dBm 1.85 GHz class-D outphasing RF PA in 130nm CMOS for WCDMA/LTE

Phase Predistortion of a Class-D Outphasing RF Amplifier in 90 nm CMOS

Analysis of a 5.5-V Class-D Stage Used in + 30-dBm Outphasing RF PAs in 130- and 65-nm CMOS

Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

Low-Power Delta-Sigma Modulators for Medical Applications

A 3.5GHz 32mW 150nm multiphase clock generator for high-performance microprocessors

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for medical implant devices

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