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An Efficient Interface for the Integration of IoT Devices with Smart Grids

Sensors (Basel, Switzerland), 2020-05, Vol.20 (10), p.2849

2020

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A Review of Techniques for Implementing Elliptic Curve Point Multiplication on Hardware

Journal of sensor and actuator networks, 2021-03, Vol.10 (1), p.3

2021

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Performance and Security Evaluation on a Blockchain Architecture for License Plate Recognition Systems

Applied sciences, 2021-02, Vol.11 (3), p.1255

2021

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Hyperspectral Image Classification: An Analysis Employing CNN, LSTM, Transformer, and Attention Mechanism

IEEE access, 2023, Vol.11, p.24835-24850

2023

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Worst-Case Communication Time Analysis for On-Chip Networks With Finite Buffers

IEEE access, 2023, Vol.11, p.25120-25131

2023

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Experimental data from the simulation of on-chip communication architectures using RedScarf simulation environment

Data in brief, 2019-12, Vol.27, p.104725-104725, Article 104725

2019

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Mechanisms to Provide Fault Tolerance to a Network-on-Chip

Revista IEEE América Latina, 2017-06, Vol.15 (6), p.1034-1042

2017

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A Hardware Accelerator for Onboard Spatial Resolution Enhancement of Hyperspectral Images

IEEE geoscience and remote sensing letters, 2021-10, Vol.18 (10), p.1796-1800

2021

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A real-time SVM-based hardware accelerator for hyperspectral images classification in FPGA

Microprocessors and microsystems, 2024-02, Vol.104, p.104998, Article 104998

2024

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Reliability analysis of a fault-tolerant RISC-V system-on-chip

Microelectronics and reliability, 2021-10, Vol.125, p.114346, Article 114346

2021

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Confidentiality and Authenticity in a Platform Based on Network-on-Chip

2017 VII Brazilian Symposium on Computing Systems Engineering (SBESC), 2017, p.225-230

2017

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Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router

2019 IEEE Latin American Test Symposium (LATS), 2019, p.1-6

2019

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Digital Statelessness: The Gap Between Technological Advancement and the Full Guarantee of Human Rights

New Trends in Disruptive Technologies, Tech Ethics and Artificial Intelligence, p.178-189

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Security mechanisms to improve the availability of a Network-on-Chip

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS), 2013, p.609-612

2013

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Avaliação Empírica da Proposta Interdisciplinar de Uso dos Processadores BIP

Revista brasileira de informática na educação, 2015-06, Vol.23 (2), p.99

2015

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SPIN: a scalable, packet switched, on-chip micro-network

2003 Design, Automation and Test in Europe Conference and Exhibition, 2003, p.70-73 suppl.

2003

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A Low-Cost Fault-Tolerant RISC-V Processor for Space Systems

2020 15th Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2020, p.1-5

2020

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Bipide – Ambiente de Desenvolvimento Integrado para a Arquitetura dos Processadores BIP

Revista brasileira de informática na educação, 2010-01, Vol.18 (1), p.32-43

2010

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Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router

2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2021, p.1-6

2021

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Data Transmission Performance Analysis with Smart Grid Protocol and Cryptography Algorithms

2018 13th IEEE International Conference on Industry Applications (INDUSCON), 2018, p.482-486

2018

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RASoC: a router soft-core for networks-on-chip

Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004, Vol.3, p.198-203 Vol.3

2004

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An Architecture for Delivering Graphical Web Applications in Constrained IoT Devices

2019 IX Brazilian Symposium on Computing Systems Engineering (SBESC), 2019, p.1-8

2019

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Deadline, Energy and Buffer-Aware Task Mapping Optimization in NoC-Based SoCs Using Genetic Algorithms

2017 VII Brazilian Symposium on Computing Systems Engineering (SBESC), 2017, p.86-93

2017

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RedScarf: A User-Friendly Multi-Platform Network-on-Chip Simulator

2017 VII Brazilian Symposium on Computing Systems Engineering (SBESC), 2017, p.71-78

2017

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Implementation of Techniques for Fault Tolerance in a Network-on-Chip

2010 11th Symposium on Computing Systems, 2010, p.80-87

2010

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An Efficient Interface for the Integration of IoT Devices with Smart Grids

A Review of Techniques for Implementing Elliptic Curve Point Multiplication on Hardware

Performance and Security Evaluation on a Blockchain Architecture for License Plate Recognition Systems

Hyperspectral Image Classification: An Analysis Employing CNN, LSTM, Transformer, and Attention Mechanism

Worst-Case Communication Time Analysis for On-Chip Networks With Finite Buffers

Experimental data from the simulation of on-chip communication architectures using RedScarf simulation environment

Mechanisms to Provide Fault Tolerance to a Network-on-Chip

A Hardware Accelerator for Onboard Spatial Resolution Enhancement of Hyperspectral Images

A real-time SVM-based hardware accelerator for hyperspectral images classification in FPGA

Reliability analysis of a fault-tolerant RISC-V system-on-chip

Confidentiality and Authenticity in a Platform Based on Network-on-Chip

Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router

Digital Statelessness: The Gap Between Technological Advancement and the Full Guarantee of Human Rights

Security mechanisms to improve the availability of a Network-on-Chip

Avaliação Empírica da Proposta Interdisciplinar de Uso dos Processadores BIP

SPIN: a scalable, packet switched, on-chip micro-network

A Low-Cost Fault-Tolerant RISC-V Processor for Space Systems

Bipide – Ambiente de Desenvolvimento Integrado para a Arquitetura dos Processadores BIP

Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router

Data Transmission Performance Analysis with Smart Grid Protocol and Cryptography Algorithms

RASoC: a router soft-core for networks-on-chip

An Architecture for Delivering Graphical Web Applications in Constrained IoT Devices

Deadline, Energy and Buffer-Aware Task Mapping Optimization in NoC-Based SoCs Using Genetic Algorithms

RedScarf: A User-Friendly Multi-Platform Network-on-Chip Simulator

Implementation of Techniques for Fault Tolerance in a Network-on-Chip

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