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Nonvolatile Silicon Memory Using GeO x -Cladded Ge Quantum Dots Self-Assembled on SiO2 and Lattice-Matched II–VI Tunnel Insulator

Journal of electronic materials, 2011-08, Vol.40 (8), p.1769-1774

2011

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Spatial Wavefunction-Switched (SWS) InGaAs FETs with II–VI Gate Insulators

Journal of electronic materials, 2011-08, Vol.40 (8), p.1717-1726

2011

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Voltage-Dependent Charge Storage in Cladded Zn0.56Cd0.44Se Quantum Dot MOS Capacitors for Multibit Memory Applications

Journal of electronic materials, 2013-11, Vol.42 (11), p.3267-3274

2013

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Nonvolatile Memories Using Quantum Dot (QD) Floating Gates Assembled on II–VI Tunnel Insulators

Journal of electronic materials, 2010-07, Vol.39 (7), p.903-907

2010

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Fabrication and Simulation of an Indium Gallium Arsenide Quantum-Dot-Gate Field-Effect Transistor (QDG-FET) with ZnMgS as a Tunnel Gate Insulator

Journal of electronic materials, 2013-11, Vol.42 (11), p.3259-3266

2013

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Nonvolatile Memory Effect in Indium Gallium Arsenide-Based Metal–Oxide–Semiconductor Devices Using II–VI Tunnel Insulators

Journal of electronic materials, 2011-08, Vol.40 (8), p.1685-1688

2011

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Nonvolatile Silicon Memory Using GeOx-Cladded Ge Quantum Dots Self-Assembled on SiO2 and Lattice-Matched II–VI Tunnel Insulator

Journal of electronic materials, 2011, Vol.40 (8), p.1769-1774

2011

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Voltage-Dependent Charge Storage in Cladded Zn^sub 0.56^Cd^sub 0.44^Se Quantum Dot MOS Capacitors for Multibit Memory Applications

Journal of electronic materials, 2013-11, Vol.42 (11), p.3267

2013

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Nonvolatile Silicon Memory Using GeO^sub x^-Cladded Ge Quantum Dots Self-Assembled on SiO^sub 2^ and Lattice-Matched II-VI Tunnel Insulator

Journal of electronic materials, 2011-08, Vol.40 (8), p.1769

2011

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Core-Shell Zn sub(x)cd sub(1-x)Se/Zn sub(y)Cd sub(1-y)Se Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

Journal of electronic materials, 2011-08, Vol.40 (8), p.1699-1699

2011

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Nonvolatile Silicon Memory Using GeO sub(x)-Cladded Ge Quantum Dots Self-Assembled on SiO sub(2) and Lattice-Matched II-VI Tunnel Insulator

Journal of electronic materials, 2011-08, Vol.40 (8), p.1769-1769

2011

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A 14 nm SoC platform technology featuring 2 super(nd) generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um super(2) SRAM cells, optimized for low power, high performance and high density SoC products

Digest of technical papers - Symposium on VLSI Technology, 2015-06, p.T12-T13

2015

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A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products

2015 Symposium on VLSI Technology (VLSI Technology), 2015, p.T12-T13

2015

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A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products

2015 Symposium on VLSI Circuits (VLSI Circuits), 2015, p.T12-T13

2015

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A 14 nm SoC platform technology featuring 2 super(nd) generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um super(2) SRAM cells, optimized for low power, high performance and high density SoC products

2015 Symposium on VLSI Circuits (VLSI Circuits), 2015-06, p.T12-T13

2015

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ZnxCd1−xSe/ ZnyCd1−ySe quantum dot floating gate nonvolatile memory

2009 International Semiconductor Device Research Symposium, 2009, p.1-2

2009

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Core-Shell Zn^sub x^Cd^sub 1-x^Se/Zn^sub y^Cd^sub 1-y^Se Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

Journal of electronic materials, 2011-08, Vol.40 (8), p.1699

2011

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Core–Shell Zn x Cd1−x Se/Zn y Cd1−y Se Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

Journal of electronic materials, 2011-08, Vol.40 (8), p.1699-1705

2011

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Core–Shell ZnxCd1−xSe/ZnyCd1−ySe Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

Journal of electronic materials, 2011, Vol.40 (8), p.1699-1705

2011

Volltextzugriff (PDF)

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Nonvolatile Silicon Memory Using GeO x -Cladded Ge Quantum Dots Self-Assembled on SiO2 and Lattice-Matched II–VI Tunnel Insulator

Spatial Wavefunction-Switched (SWS) InGaAs FETs with II–VI Gate Insulators

Voltage-Dependent Charge Storage in Cladded Zn0.56Cd0.44Se Quantum Dot MOS Capacitors for Multibit Memory Applications

Nonvolatile Memories Using Quantum Dot (QD) Floating Gates Assembled on II–VI Tunnel Insulators

Fabrication and Simulation of an Indium Gallium Arsenide Quantum-Dot-Gate Field-Effect Transistor (QDG-FET) with ZnMgS as a Tunnel Gate Insulator

Nonvolatile Memory Effect in Indium Gallium Arsenide-Based Metal–Oxide–Semiconductor Devices Using II–VI Tunnel Insulators

Nonvolatile Silicon Memory Using GeOx-Cladded Ge Quantum Dots Self-Assembled on SiO2 and Lattice-Matched II–VI Tunnel Insulator

Voltage-Dependent Charge Storage in Cladded Zn^sub 0.56^Cd^sub 0.44^Se Quantum Dot MOS Capacitors for Multibit Memory Applications

Nonvolatile Silicon Memory Using GeO^sub x^-Cladded Ge Quantum Dots Self-Assembled on SiO^sub 2^ and Lattice-Matched II-VI Tunnel Insulator

Core-Shell Zn sub(x)cd sub(1-x)Se/Zn sub(y)Cd sub(1-y)Se Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

Nonvolatile Silicon Memory Using GeO sub(x)-Cladded Ge Quantum Dots Self-Assembled on SiO sub(2) and Lattice-Matched II-VI Tunnel Insulator

A 14 nm SoC platform technology featuring 2 super(nd) generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um super(2) SRAM cells, optimized for low power, high performance and high density SoC products

A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products

A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products

A 14 nm SoC platform technology featuring 2 super(nd) generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um super(2) SRAM cells, optimized for low power, high performance and high density SoC products

ZnxCd1−xSe/ ZnyCd1−ySe quantum dot floating gate nonvolatile memory

Core-Shell Zn^sub x^Cd^sub 1-x^Se/Zn^sub y^Cd^sub 1-y^Se Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

Core–Shell Zn x Cd1−x Se/Zn y Cd1−y Se Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

Core–Shell ZnxCd1−xSe/ZnyCd1−ySe Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

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