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Architecture of Cobweb-Based Redundant TSV for Clustered Faults

IEEE transactions on very large scale integration (VLSI) systems, 2020-07, Vol.28 (7), p.1736-1739

2020

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Buddhist Architecture in East Asia

2022

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Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment

IEEE transactions on computers, 2020-06, Vol.69 (6), p.789-799

2020

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LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2938-2951

2020

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Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology

IEEE transactions on very large scale integration (VLSI) systems, 2017-06, Vol.25 (6), p.1978-1982

2017

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Spatialization of Imperial Power: Spatial Reconstruction and Power Operation of Jinshan Temple during the Southern Inspection Tours of Emperor Kangxi

Religions (Basel, Switzerland ), 2023-12, Vol.15 (1), p.7

2023

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Body, Scale, and Space: Study on the Spatial Construction of Mogao Cave 254

Religions (Basel, Switzerland ), 2023-07, Vol.14 (7), p.953

2023

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Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC

IEEE transactions on circuits and systems. II, Express briefs, 2020-11, Vol.67 (11), p.2657-2661

2020

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Legends, Inspirations and Space: Landscape Sacralization of the Sacred Site Mount Putuo

Religions (Basel, Switzerland ), 2021-12, Vol.12 (12), p.1050

2021

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A Treatise on the Garden of Jiangnan: A Study on the Art of Chinese Classical Garden

1, 2022

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High-performance, low-cost, and highly reliable radiation hardened latch design

Electronics letters, 2016-01, Vol.52 (2), p.139-141

2016

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Statistical analysis of energy consumption patterns on the heat demand of buildings in district heating systems

Energy and buildings, 2014-12, Vol.85, p.464-472

2014

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Evaluation and Test of Production Defects in Hardened Latches

IEICE Transactions on Information and Systems, 2022/05/01, Vol.E105.D(5), pp.996-1009

2022

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A Methodology for Characterization of SET Propagation in SRAM-Based FPGAs

IEEE transactions on nuclear science, 2016-12, Vol.63 (6), p.2985-2992

2016

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Performance and emissions of pre-mixed and post-mixed combustion systems with a casting aluminum-silicon alloy (CASA) condensing gas boiler

Heat and mass transfer, 2020-02, Vol.56 (2), p.651-662

2020

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T2FA: Transparent Two-Factor Authentication

IEEE access, 2018-01, Vol.6, p.32677-32686

2018

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Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications

Journal of electronic testing, 2021-08, Vol.37 (4), p.489-502

2021

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Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets

IEEE access, 2019, Vol.7, p.176188-176196

2019

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A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology

IEICE transactions on electronics, 2015, Vol.E98.C (12), p.1171-1178

2015

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Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm

IEEE access, 2020-01, Vol.8, p.1-1

2020

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A ReRAM-Based Non-Volatile and Radiation-Hardened Latch Design

Micromachines (Basel), 2022-10, Vol.13 (11), p.1802

2022

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Design of a Radiation Hardened Latch for Low-Power Circuits

2014 IEEE 23rd Asian Test Symposium, 2014, p.19-24

2014

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Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory

2019 IEEE 37th VLSI Test Symposium (VTS), 2019, p.1-6

2019

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Highly Robust Double Node Upset Resilient Hardened Latch Design

IEICE transactions on electronics, 2017-01, Vol.E100.C (5), p.496-503

2017

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A Region-Based Through-Silicon via Repair Method for Clustered Faults

IEICE transactions on electronics, 2017-01, Vol.E100.C (12), p.1108-1117

2017

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Architecture of Cobweb-Based Redundant TSV for Clustered Faults

Buddhist Architecture in East Asia

Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology

Spatialization of Imperial Power: Spatial Reconstruction and Power Operation of Jinshan Temple during the Southern Inspection Tours of Emperor Kangxi

Body, Scale, and Space: Study on the Spatial Construction of Mogao Cave 254

Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC

Legends, Inspirations and Space: Landscape Sacralization of the Sacred Site Mount Putuo

A Treatise on the Garden of Jiangnan: A Study on the Art of Chinese Classical Garden

High-performance, low-cost, and highly reliable radiation hardened latch design

Statistical analysis of energy consumption patterns on the heat demand of buildings in district heating systems

Evaluation and Test of Production Defects in Hardened Latches

A Methodology for Characterization of SET Propagation in SRAM-Based FPGAs

Performance and emissions of pre-mixed and post-mixed combustion systems with a casting aluminum-silicon alloy (CASA) condensing gas boiler

T2FA: Transparent Two-Factor Authentication

Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications

Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets

A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology

Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm

A ReRAM-Based Non-Volatile and Radiation-Hardened Latch Design

Design of a Radiation Hardened Latch for Low-Power Circuits

Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory

Highly Robust Double Node Upset Resilient Hardened Latch Design

A Region-Based Through-Silicon via Repair Method for Clustered Faults

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