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Digital in-memory stochastic computing architecture for vector-matrix multiplication

Frontiers in nanotechnology, 2023-07, Vol.5

2023

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A Low Power Self-healing Resilient Microarchitecture for PVT Variability Mitigation

IEEE transactions on circuits and systems. I, Regular papers, 2018-06, Vol.65 (6), p.1909-1918

2018

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A 1T1R+2T Analog Content-Addressable Memory Pixel for Online Template Matching

2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5

2023

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ERSUT: A Self-Healing Architecture for Mitigating PVT Variations Without Pipeline Flushing

IEEE transactions on circuits and systems. II, Express briefs, 2016-11, Vol.63 (11), p.1069-1073

2016

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High-Density Digital RRAM-based Memory with Bit-line Compute Capability

2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022, p.1199-1200

2022

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Layout-Based Evaluation of Read/Write Performance of SOT-MRAM and SOTFET-RAM

ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC), 2021, p.283-286

2021

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PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks

2019 IEEE 37th International Conference on Computer Design (ICCD), 2019, p.437-445

2019

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EVE: Ephemeral Vector Engines

2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023, p.691-704

2023

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Towards a Reconfigurable Bit-Serial/Bit-Parallel Vector Accelerator using In-Situ Processing-In-SRAM

2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, p.1-5

2020

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Bent-Pyramid: Towards A Quasi-Stochastic Data Representation for AI Hardware

2023 21st IEEE Interregional NEWCAS Conference (NEWCAS), 2023, p.1-5

2023

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CIFER: A Cache-Coherent 12nm 16mm2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable eFPGA

IEEE solid-state circuits letters, 2023-08, p.1-1

2023

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A CMOS-based Characterisation Platform for Emerging RRAM Technologies

2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022, p.75-79

2022

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CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA

2023 IEEE Custom Integrated Circuits Conference (CICC), 2023, p.1-2

2023

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CIFER: A Cache-Coherent 12-nm 16-mm 2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm 2 Synthesizable eFPGA

IEEE solid-state circuits letters, 2023, Vol.6, p.229-232

2023

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CIFER: A Cache-Coherent 12-nm 16-mm2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable eFPGA

IEEE solid-state circuits letters, 2023-01, Vol.6, p.229

2023

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Implementing Low-Diameter On-Chip Networks for Manycore Processors Using a Tiled Physical Design Methodology

2020 14th IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2020, p.1-8

2020

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Power efficient AES core for IoT constrained devices implemented in 130nm CMOS

2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, p.1-4

2017

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Variability mitigation using correction function technique

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS), 2013, p.293-296

2013

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Hardware Pessimistic Run-Time Profiling for a Self-Reconfigurable Embedded Processor Architecture

2010 International Conference on Reconfigurable Computing and FPGAs, 2010, p.162-167

2010

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Towards a self-reconfigurable embedded processor architecture

2009 International Conference on Computer Engineering & Systems, 2009, p.21-26

2009

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Digital in-memory stochastic computing architecture for vector-matrix multiplication

A Low Power Self-healing Resilient Microarchitecture for PVT Variability Mitigation

A 1T1R+2T Analog Content-Addressable Memory Pixel for Online Template Matching

ERSUT: A Self-Healing Architecture for Mitigating PVT Variations Without Pipeline Flushing

High-Density Digital RRAM-based Memory with Bit-line Compute Capability

Layout-Based Evaluation of Read/Write Performance of SOT-MRAM and SOTFET-RAM

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks

EVE: Ephemeral Vector Engines

Towards a Reconfigurable Bit-Serial/Bit-Parallel Vector Accelerator using In-Situ Processing-In-SRAM

Bent-Pyramid: Towards A Quasi-Stochastic Data Representation for AI Hardware

CIFER: A Cache-Coherent 12nm 16mm2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable eFPGA

A CMOS-based Characterisation Platform for Emerging RRAM Technologies

CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA

CIFER: A Cache-Coherent 12-nm 16-mm 2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm 2 Synthesizable eFPGA

CIFER: A Cache-Coherent 12-nm 16-mm2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable eFPGA

Implementing Low-Diameter On-Chip Networks for Manycore Processors Using a Tiled Physical Design Methodology

Power efficient AES core for IoT constrained devices implemented in 130nm CMOS

Variability mitigation using correction function technique

Hardware Pessimistic Run-Time Profiling for a Self-Reconfigurable Embedded Processor Architecture

Towards a self-reconfigurable embedded processor architecture

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