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Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications

Solid-state electronics, 2023-10, Vol.208, p.108729, Article 108729

2023

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InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec sub-threshold swing at room temperature

Applied physics letters, 2016-12, Vol.109 (24)

2016

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Experimental silicon tunnel-FET device model applied to design a Gm-C filter

Semiconductor science and technology, 2020-09, Vol.35 (9), p.95029

2020

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Comparison between proton irradiated triple gate SOI TFETS and finfets from a TID point of view

Semiconductor science and technology, 2019-06, Vol.34 (6), p.65003

2019

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Experimental analysis and improvement of the DC method for self-heating estimation

Solid-state electronics, 2019-09, Vol.159, p.171-176

2019

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Performance of differential pair circuits designed with line tunnel FET devices at different temperatures

Semiconductor science and technology, 2018-07, Vol.33 (7), p.75012

2018

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Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes

Semiconductor science and technology, 2016-10, Vol.31 (11), p.114002

2016

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Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures

Semiconductor science and technology, 2017-05, Vol.32 (5), p.55015

2017

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Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures

Semiconductor science and technology, 2016-05, Vol.31 (5), p.55001

2016

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Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias

Semiconductor science and technology, 2019-03, Vol.34 (3), p.35003

2019

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Analog performance of standard and uniaxial strained triple-gate SOI FinFETs under x-ray radiation

Semiconductor science and technology, 2014-12, Vol.29 (12), p.125015

2014

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Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs

Solid-state electronics, 2015-01, Vol.103, p.209-215

2015

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Gate dielectric material influence on DC behavior of MO(I)SHEMT devices operating up to 150 °C

Solid-state electronics, 2021-11, Vol.185, p.108091, Article 108091

2021

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NW-TFET analog performance for different Ge source compositions

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013, p.1-2

2013

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Back bias influence on analog performance of pTFET

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013, p.1-2

2013

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Biaxial + uniaxial stress effectiveness in tri-gate SOI nMOSFETs with variable fin dimensions

2012 IEEE International SOI Conference (SOI), 2012, p.1-2

2012

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Fin shape influence on the analog performance of standard and strained MuGFETs

2010 IEEE International SOI Conference (SOI), 2010, p.1-2

2010

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Electron valence-band tunnelling excess noise in twin-gate silicon-on-insulator MOSFETs

Solid-state electronics, 2006, Vol.50 (1), p.52-57

2006

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Experimental analog performance of pTFETs as a function of temperature

2012 IEEE International SOI Conference (SOI), 2012, p.1-2

2012

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Performance evaluation of Tunnel-FET basic amplifier circuits

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), 2019, p.21-24

2019

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Uniaxial stress efficiency for different fin dimensions of triple-gate SOI nMOSFETs

IEEE 2011 International SOI Conference, 2011, p.1-2

2011

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Comparison between nMOS and pMOS Omega-gate nanowire down to 10nm width as a function of back gate bias

Semiconductor science and technology, 2019-03, Vol.34 (3)

2019

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Comparison between nMOS and pMOS -gate nanowire down to 10 nm width as a function of back gate bias

Semiconductor science and technology, 2019-01, Vol.34 (3)

2019

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Optimization of the Dual-Technology Back-Enhanced Field Effect Transistor

2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2020, p.1-4

2020

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AlGaN/GaN MISHEMT analysis from an analog point of view up to 150°C

2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2020, p.1-4

2020

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Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications

InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec sub-threshold swing at room temperature

Experimental silicon tunnel-FET device model applied to design a Gm-C filter

Comparison between proton irradiated triple gate SOI TFETS and finfets from a TID point of view

Experimental analysis and improvement of the DC method for self-heating estimation

Performance of differential pair circuits designed with line tunnel FET devices at different temperatures

Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes

Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures

Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures

Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias

Analog performance of standard and uniaxial strained triple-gate SOI FinFETs under x-ray radiation

Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs

Gate dielectric material influence on DC behavior of MO(I)SHEMT devices operating up to 150 °C

NW-TFET analog performance for different Ge source compositions

Back bias influence on analog performance of pTFET

Biaxial + uniaxial stress effectiveness in tri-gate SOI nMOSFETs with variable fin dimensions

Fin shape influence on the analog performance of standard and strained MuGFETs

Electron valence-band tunnelling excess noise in twin-gate silicon-on-insulator MOSFETs

Experimental analog performance of pTFETs as a function of temperature

Performance evaluation of Tunnel-FET basic amplifier circuits

Uniaxial stress efficiency for different fin dimensions of triple-gate SOI nMOSFETs

Comparison between nMOS and pMOS Omega-gate nanowire down to 10nm width as a function of back gate bias

Comparison between nMOS and pMOS -gate nanowire down to 10 nm width as a function of back gate bias

Optimization of the Dual-Technology Back-Enhanced Field Effect Transistor

AlGaN/GaN MISHEMT analysis from an analog point of view up to 150°C

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