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39 000-Subexposures/s Dual-ADC CMOS Image Sensor With Dual-Tap Coded-Exposure Pixels for Single-Shot HDR and 3-D Computational Imaging

IEEE journal of solid-state circuits, 2023-11, Vol.58 (11), p.1-14

2023

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Noema: Hardware-Efficient Template Matching for Neural Population Pattern Detection

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021, p.522-534

2021

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Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs

2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 2017, p.41-48

2017

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Modular Switched Multiported SRAM-Based Memories

ACM transactions on reconfigurable technology and systems, 2016-09, Vol.9 (3), p.1-26

2016

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Synthesizable Synchronization FIFOs Utilizing the Asynchronous Pulse-Based Handshake Protocol

2020 IEEE Nordic Circuits and Systems Conference (NorCAS), 2020, p.1-7

Abdelhadi, Ameer M.S.

2020

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Timing–driven variation–aware synthesis of hybrid mesh/tree clock distribution networks

Integration (Amsterdam), 2013-09, Vol.46 (4), p.382-391

2013

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Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOs

2021 31st International Conference on Field-Programmable Logic and Applications (FPL), 2021, p.312-318

2021

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Revisiting Deep Learning Parallelism: Fine-Grained Inference Engine Utilizing Online Arithmetic

2019 International Conference on Field-Programmable Technology (ICFPT), 2019, p.383-386

2019

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Reconfigurable Synthesizable Synchronization FIFOs

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2021, p.272-272

2021

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Mokey: enabling narrow fixed-point inference for out-of-the-box floating-point transformer models

Proceedings of the 49th Annual International Symposium on Computer Architecture, 2022, p.888-901

2022

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Adversarial Hardware With Functional and Topological Camouflage

IEEE transactions on circuits and systems. II, Express briefs, 2021-05, Vol.68 (5), p.1685-1689

2021

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Accelerated Approximate Nearest Neighbors Search Through Hierarchical Product Quantization

2019 International Conference on Field-Programmable Technology (ICFPT), 2019, p.90-98

2019

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Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories

2018 28th International Conference on Field Programmable Logic and Applications (FPL), 2018, p.243-2437

2018

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A Multi-ported Memory Compiler Utilizing True Dual-Port BRAMs

2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2016, p.140-147

2016

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Modular SRAM-Based Binary Content-Addressable Memories

2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, 2015, p.207-214

2015

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Deep and narrow binary content-addressable memories using FPGA-based BRAMs

2014 International Conference on Field-Programmable Technology (FPT), 2014, p.318-321

2014

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A 39,000 Subexposures/s CMOS Image Sensor with Dual-tap Coded-exposure Data-memory Pixel for Adaptive Single-shot Computational Imaging

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.78-79

2022

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Timingadriven variationaaware synthesis of hybrid mesh/tree clock distribution networks

Integration (Amsterdam), 2013-09, Vol.46 (4), p.382-391

2013

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High-Throughput Synthesizable Synchronization FIFOs for Mixed-Timing NoCs

2020 13th International Workshop on Network on Chip Architectures (NoCArc), 2020, p.1-6

Abdelhadi, Ameer M.S.

2020

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A Massive-Scale Brain Activity Decoding Chip

2022 IEEE Hot Chips 34 Symposium (HCS), 2022, p.1-65

2022

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Marple: Scalable Spike Sorting for Untethered Brain-Machine Interfacing

Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2, 2024, p.666-682

2024

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Atalanta: A Bit is Worth a “Thousand” Tensor Values

Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2, 2024, p.85-102

2024

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Modular multi-ported SRAM-based memories

Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays, 2014, p.35-44

2014

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Timing-driven variation-aware nonuniform clock mesh synthesis

Proceedings of the 20th symposium on Great lakes symposium on VLSI, 2010, p.15-20

2010

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Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations

2011 International Conference on Reconfigurable Computing and FPGAs, 2011, p.20-26

2011

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39 000-Subexposures/s Dual-ADC CMOS Image Sensor With Dual-Tap Coded-Exposure Pixels for Single-Shot HDR and 3-D Computational Imaging

Noema: Hardware-Efficient Template Matching for Neural Population Pattern Detection

Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs

Modular Switched Multiported SRAM-Based Memories

Synthesizable Synchronization FIFOs Utilizing the Asynchronous Pulse-Based Handshake Protocol

Timing–driven variation–aware synthesis of hybrid mesh/tree clock distribution networks

Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOs

Revisiting Deep Learning Parallelism: Fine-Grained Inference Engine Utilizing Online Arithmetic

Reconfigurable Synthesizable Synchronization FIFOs

Mokey: enabling narrow fixed-point inference for out-of-the-box floating-point transformer models

Adversarial Hardware With Functional and Topological Camouflage

Accelerated Approximate Nearest Neighbors Search Through Hierarchical Product Quantization

Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories

A Multi-ported Memory Compiler Utilizing True Dual-Port BRAMs

Modular SRAM-Based Binary Content-Addressable Memories

Deep and narrow binary content-addressable memories using FPGA-based BRAMs

A 39,000 Subexposures/s CMOS Image Sensor with Dual-tap Coded-exposure Data-memory Pixel for Adaptive Single-shot Computational Imaging

Timingadriven variationaaware synthesis of hybrid mesh/tree clock distribution networks

High-Throughput Synthesizable Synchronization FIFOs for Mixed-Timing NoCs

A Massive-Scale Brain Activity Decoding Chip

Marple: Scalable Spike Sorting for Untethered Brain-Machine Interfacing

Atalanta: A Bit is Worth a “Thousand” Tensor Values

Modular multi-ported SRAM-based memories

Timing-driven variation-aware nonuniform clock mesh synthesis

Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations

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