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Editorial TVLSI Positioning-Continuing and Accelerating an Upward Trajectory

IEEE transactions on very large scale integration (VLSI) systems, 2019-02, Vol.27 (2), p.253-280

Alioto, Massimo

2019

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Coverage metrics for verification of concurrent SystemC designs using mutation testing

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT), 2010, p.75-81

2010

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Guest Editorial: Test and Verification Challenges for Future Microprocessors and SoC Designs

Journal of electronic testing, 2013-10, Vol.29 (5), p.621-623

2013

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An experiment of burn-in time reduction based on parametric test analysis

2012 IEEE International Test Conference, 2012, p.1-10

2012

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A pattern mining framework for inter-wafer abnormality analysis

2013 IEEE International Test Conference (ITC), 2013, p.1-10

2013

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Forward prediction based on wafer sort data - A case study

2011 IEEE International Test Conference, 2011, p.1-10

2011

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Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch

Design Automation Conference, 2010, p.374-379

2010

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Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG

Journal of electronic testing, 2005-10, Vol.21 (5), p.495-502

2005

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Functional Testing of Semiconductor Random Access Memories

ACM computing surveys, 1983-09, Vol.15 (3), p.175-198

1983

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Design-silicon timing correlation: a data mining perspective

Annual ACM IEEE Design Automation Conference: Proceedings of the 44th annual conference on Design automation : San Diego, California; 04-08 June 2007, 2007, p.384-389

2007

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Formal verification of content addressable memories using symbolic trajectory evaluation

Annual ACM IEEE Design Automation Conference: Proceedings of the 34th annual conference on Design automation; 09-13 June 1997, 1997, p.167-172

1997

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Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step

Design, Automation, and Test in Europe: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1; 03-07 Mar. 2003, 2003, p.10328-10328

2003

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Yield optimization using advanced statistical correlation methods

2014 International Test Conference, 2014, p.1-10

2014

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Oscillation Ring Delay Test for High Performance Microprocessors

Journal of electronic testing, 2000-02, Vol.16 (1-2), p.147

2000

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Data Mining In EDA - Basic Principles, Promises, and Constraints

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 2014, p.1-6

2014

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Screening customer returns with multivariate test analysis

2012 IEEE International Test Conference, 2012, p.1-10

2012

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On path-based learning and its applications in delay test and diagnosis

Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004, 2004, p.492-497

2004

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MTV 2019 Preface

2019 20th International Workshop on Microprocessor/SoC Test, Security and Verification (MTV), 2019, p.7-8

2019

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On Efficiently Producing Quality Tests for Custom Circuits in PowerPC(TM) Microprocessors

Journal of electronic testing, 2000-02, Vol.16 (1-2), p.121

2000

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Validating Power Architecture™ Technology-Based MPSoCs Through Executable Specifications : Design verification and validation

IEEE transactions on very large scale integration (VLSI) systems, 2008, Vol.16 (4), p.388-396

2008

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Design rewiring using ATPG

Proceedings - International Test Conference, 2002, p.223-232

2002

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On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays

ACM transactions on design automation of electronic systems, 1998-10, Vol.3 (4), p.524-532

1998

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Combining ATPG and symbolic simulation for efficient validation of embedded array systems

Proceedings - International Test Conference, 2002, p.203-212

2002

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Validating Power Architecture™ Technology-Based MPSoCs Through Executable Specifications

IEEE transactions on very large scale integration (VLSI) systems, 2008-04, Vol.16 (4), p.388-396

2008

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Introduction to special section on verification challenges in the concurrent world

ACM transactions on design automation of electronic systems, 2012-06, Vol.17 (3), p.1-3

2012

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Editorial TVLSI Positioning-Continuing and Accelerating an Upward Trajectory

Coverage metrics for verification of concurrent SystemC designs using mutation testing

Guest Editorial: Test and Verification Challenges for Future Microprocessors and SoC Designs

An experiment of burn-in time reduction based on parametric test analysis

A pattern mining framework for inter-wafer abnormality analysis

Forward prediction based on wafer sort data - A case study

Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch

Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG

Functional Testing of Semiconductor Random Access Memories

Design-silicon timing correlation: a data mining perspective

Formal verification of content addressable memories using symbolic trajectory evaluation

Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step

Yield optimization using advanced statistical correlation methods

Oscillation Ring Delay Test for High Performance Microprocessors

Data Mining In EDA - Basic Principles, Promises, and Constraints

Screening customer returns with multivariate test analysis

On path-based learning and its applications in delay test and diagnosis

MTV 2019 Preface

On Efficiently Producing Quality Tests for Custom Circuits in PowerPC(TM) Microprocessors

Validating Power Architecture™ Technology-Based MPSoCs Through Executable Specifications : Design verification and validation

Design rewiring using ATPG

On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays

Combining ATPG and symbolic simulation for efficient validation of embedded array systems

Validating Power Architecture™ Technology-Based MPSoCs Through Executable Specifications

Introduction to special section on verification challenges in the concurrent world

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