UB Paderborn / Katalog / Suche / in CDI

Input and/or Output Pruning of Composite Length FFTs Using a DIF-DIT Transform Decomposition

IEEE transactions on signal processing, 2009-10, Vol.57 (10), p.4124-4128

2009

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An FPGA stereo matching unit based on fuzzy logic

Microprocessors and microsystems, 2016-05, Vol.42, p.87-99

2016

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Visualization of a supersonic air micro jet by methods of dual-hologram interferometry

Experiments in fluids, 2007-06, Vol.42 (6), p.863-869

2007

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A Fuzzy Logic Approach for Stereo Matching Suited for Real-Time Processing

International journal of computer applications, 2015-01, Vol.113 (2), p.1-8

2015

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Using a Scaling Factor in O(1/N) for the fixed-point implementation of the second-order goertzel filter

2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012, p.3218-3221

2012

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FPGA Processor for Real-Time Optical Flow Computation

Field Programmable Logic and Application, 2003, p.1103-1106

2003

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FPGA-Based Configurable Systolic Architecture for Window-Based Image Processing

EURASIP Journal on Applied Signal Processing, 2005-05, Vol.2005 (7), p.1024-1034, Article 264713

2005

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Real-time image processing with a compact FPGA-based systolic architecture

Real-time imaging, 2004-06, Vol.10 (3), p.177-187

2004

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Configurable Hardware Architecture for Real-Time Window-Based Image Processing

Field Programmable Logic and Application, 2003, p.1008-1011

2003

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FPGA Based High Density Spiking Neural Network Array

Field Programmable Logic and Application, 2003, p.1053-1056

2003

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A SOLAR MID-INFRARED TELESCOPE

Revista mexicana de astronomía y astrofísica, 2019-04, Vol.55 (1), p.11-16

2019

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3D recovery with free hand camera motion

Sixth Mexican International Conference on Computer Science (ENC'05), 2005, p.145-151

2005

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Super-resolution with integrated radial distortion correction

Sixth Mexican International Conference on Computer Science (ENC'05), 2005, p.165-172

2005

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An FPGA architecture for high speed edge and corner detection

Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception, 2000, p.112-116

2000

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Compact Spiking Neural Network Implementation in FPGA

Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing, 2000, p.270-276

2000

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A reconfigurable vision system for real-time applications

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings, 2002, p.286-289

2002

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FPGA based computer vision camera

International Symposium on Field Programmable Gate Arrays: Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays; 21-23 Feb. 1999, 1999, p.248-248

1999

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Compact FPGA-based systolic array architecture suitable for vision systems

Fourth International Conference on Information Technology (ITNG'07), 2007, p.1008-1013

2007

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Real Time FPGA-based Architecture for Video Applications

2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006), 2006, p.1-10

2006

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Customizable FPGA-based architecture for video applications in real time

2006 IEEE International Conference on Field Programmable Technology, 2006, p.381-384

2006

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FPGA-based customizable systolic architecture for image processing applications

2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05), 2005, p.8 pp.-3

2005

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A Hardware Architecture for Image Clustering Using Spiking Neural Networks

2012 IEEE Computer Society Annual Symposium on VLSI, 2012, p.261-266

2012

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A Low-Level Image Processing Algorithms Accelerator Platform

18th International Conference on Electronics, Communications and Computers (conielecomp 2008), 2008, p.117-122

2008

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Hardware implementation of Spiking Neural Network classifiers based on backpropagation-based learning algorithms

2009 International Joint Conference on Neural Networks, 2009, p.2294-2301

2009

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A population coding hardware architecture for Spiking Neural Networks applications

2009 5th Southern Conference on Programmable Logic (SPL), 2009, p.83-88

2009

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Input and/or Output Pruning of Composite Length FFTs Using a DIF-DIT Transform Decomposition

An FPGA stereo matching unit based on fuzzy logic

Visualization of a supersonic air micro jet by methods of dual-hologram interferometry

A Fuzzy Logic Approach for Stereo Matching Suited for Real-Time Processing

Using a Scaling Factor in O(1/N) for the fixed-point implementation of the second-order goertzel filter

FPGA Processor for Real-Time Optical Flow Computation

FPGA-Based Configurable Systolic Architecture for Window-Based Image Processing

Real-time image processing with a compact FPGA-based systolic architecture

Configurable Hardware Architecture for Real-Time Window-Based Image Processing

FPGA Based High Density Spiking Neural Network Array

A SOLAR MID-INFRARED TELESCOPE

3D recovery with free hand camera motion

Super-resolution with integrated radial distortion correction

An FPGA architecture for high speed edge and corner detection

Compact Spiking Neural Network Implementation in FPGA

A reconfigurable vision system for real-time applications

FPGA based computer vision camera

Compact FPGA-based systolic array architecture suitable for vision systems

Real Time FPGA-based Architecture for Video Applications

Customizable FPGA-based architecture for video applications in real time

FPGA-based customizable systolic architecture for image processing applications

A Hardware Architecture for Image Clustering Using Spiking Neural Networks

A Low-Level Image Processing Algorithms Accelerator Platform

Hardware implementation of Spiking Neural Network classifiers based on backpropagation-based learning algorithms

A population coding hardware architecture for Spiking Neural Networks applications

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