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Efficiently exploring architectural design spaces via predictive modeling

Operating Systems Review, 2006, p.195-206

2006

Volltextzugriff (PDF)

The Memristive Boltzmann Machines

IEEE MICRO, 2017, Vol.37 (3), p.22-29

2017

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Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator

IEEE journal on emerging and selected topics in circuits and systems, 2018-03, Vol.8 (1), p.86-101

2018

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Compact Model for Spin-Orbit Magnetic Tunnel Junctions

IEEE transactions on electron devices, 2016-02, Vol.63 (2), p.848-855

2016

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Architecting phase change memory as a scalable dram alternative

Proceedings of the 36th annual international symposium on Computer architecture, 2009, p.2-13

2009

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Content Aware Refresh: Exploiting the Asymmetry of DRAM Retention Errors to Reduce the Refresh Frequency of Less Vulnerable Data

IEEE transactions on computers, 2019-03, Vol.68 (3), p.362-374

2019

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Phase-Change Technology and the Future of Main Memory

IEEE MICRO, 2010-01, Vol.30 (1), p.143-143

2010

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Sanitizer: Mitigating the Impact of Expensive ECC Checks on STT-MRAM Based Main Memories

IEEE transactions on computers, 2018-06, Vol.67 (6), p.847-860

2018

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Adapting In Situ Accelerators for Sparsity with Granular Matrix Reordering

IEEE computer architecture letters, 2020-07, Vol.19 (2), p.143-146

2020

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Adaptive Compact Magnetic Tunnel Junction Model

IEEE transactions on electron devices, 2014-11, Vol.61 (11), p.3883-3891

2014

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More is less: Improving the energy efficiency of data movement via opportunistic use of sparse codes

2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2015, p.242-254

2015

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Message from Industry Track Chair HPCA 2024

2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2024, p.xxii-xxii

2024

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Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS

IEEE transactions on very large scale integration (VLSI) systems, 2016-04, Vol.24 (4), p.1266-1279

2016

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Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach

2008 41st IEEE/ACM International Symposium on Microarchitecture, 2008, p.318-329

2008

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Memristive Accelerators for Dense and Sparse Linear Algebra: From Machine Learning to High-Performance Scientific Computing

IEEE MICRO, 2019-01, Vol.39 (1), p.58-61

Ipek, Engin

2019

Volltextzugriff (PDF)

Dynamic Multicore Resource Management: A Machine Learning Approach

IEEE MICRO, 2009-09, Vol.29 (5), p.8-17

2009

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Vertical Writes: Closing the Throughput Gap between Deeply Scaled STT-MRAM and DRAM

IEEE computer architecture letters, 2018-07, Vol.17 (2), p.151-154

2018

Volltextzugriff (PDF)

Memristive Boltzmann machine: A hardware accelerator for combinatorial optimization and deep learning

2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2016, p.1-13

2016

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A Programmable Memory Controller for the DDRx Interfacing Standards

ACM transactions on computer systems, 2013-12, Vol.31 (4), p.1-31

2013

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An Approach to Performance Prediction for Parallel Applications

Euro-Par 2005 Parallel Processing, 2005, Vol.3648, p.196-205

2005

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Efficiently exploring architectural design spaces via predictive modeling

SIGPLAN notices, 2006-11, Vol.41 (11), p.195-206

2006

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Making Memristive Neural Network Accelerators Reliable

2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2018, p.52-65

2018

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Efficiently exploring architectural design spaces via predictive modeling

Operating systems review, 2006-12, Vol.40 (5), p.195-206

2006

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Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor

37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07), 2007, p.317-326

2007

Volltextzugriff (PDF)

Relationship between indoleamine 2,3-dioxygenase activity and lymphatic invasion propensity of colorectal carcinoma

World journal of gastroenterology : WJG, 2016-04, Vol.22 (13), p.3592-3601

2016

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Efficiently exploring architectural design spaces via predictive modeling

The Memristive Boltzmann Machines

Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator

Compact Model for Spin-Orbit Magnetic Tunnel Junctions

Architecting phase change memory as a scalable dram alternative

Content Aware Refresh: Exploiting the Asymmetry of DRAM Retention Errors to Reduce the Refresh Frequency of Less Vulnerable Data

Phase-Change Technology and the Future of Main Memory

Sanitizer: Mitigating the Impact of Expensive ECC Checks on STT-MRAM Based Main Memories

Adapting In Situ Accelerators for Sparsity with Granular Matrix Reordering

Adaptive Compact Magnetic Tunnel Junction Model

More is less: Improving the energy efficiency of data movement via opportunistic use of sparse codes

Message from Industry Track Chair HPCA 2024

Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS

Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach

Memristive Accelerators for Dense and Sparse Linear Algebra: From Machine Learning to High-Performance Scientific Computing

Dynamic Multicore Resource Management: A Machine Learning Approach

Vertical Writes: Closing the Throughput Gap between Deeply Scaled STT-MRAM and DRAM

Memristive Boltzmann machine: A hardware accelerator for combinatorial optimization and deep learning

A Programmable Memory Controller for the DDRx Interfacing Standards

An Approach to Performance Prediction for Parallel Applications

Efficiently exploring architectural design spaces via predictive modeling

Making Memristive Neural Network Accelerators Reliable

Efficiently exploring architectural design spaces via predictive modeling

Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor

Relationship between indoleamine 2,3-dioxygenase activity and lymphatic invasion propensity of colorectal carcinoma

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