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Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2016-07, Vol.E99.A (7), p.1400-1409

2016

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Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing

Journal of electronic testing, 2016-10, Vol.32 (5), p.601-609

2016

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IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination

IEICE Transactions on Information and Systems, 2014, Vol.E97.D(8), pp.2095-2104

2014

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Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control

2016 IEEE 25th Asian Test Symposium (ATS), 2016, p.234-239

2016

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Device-Parameter Estimation through IDDQ Signatures

IEICE Transactions on Information and Systems, 2013/02/01, Vol.E96.D(2), pp.303-313

2013

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Identification and Application of Invariant Critical Paths under NBTI Degradation

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2017-01, Vol.E100.A (12), p.2797-2806

2017

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Unsupervised recycled FPGA detection using exhaustive nearest neighbor residual analysis

Japanese Journal of Applied Physics, 2022-05, Vol.61 (SC), p.SC1076

2022

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Accelerating Machine Learning-Based Memristor Compact Modeling Using Sparse Gaussian Process

2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024, p.1-6

2024

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Gaussian process-based device model toward a unified current model across room to cryogenic temperatures

2024 IEEE 36th International Conference on Microelectronic Test Structures (ICMTS), 2024, p.1-5

2024

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Dominant Model-Parameter Determination for the Analysis of Current Imbalance Across Paralleled Power Transistors

IEEE transactions on power electronics, 2023-04, Vol.38 (4), p.4632-4646

2023

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Analog Memcapacitor by Ferroelectric Capacitor and Its Application to Spiking Neuromorphic System

IEEE transactions on electron devices, 2024-08, Vol.71 (8), p.4626-4630

2024

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A Bayesian-based process parameter estimation using IDDQ current signature

2012 IEEE 30th VLSI Test Symposium (VTS), 2012, p.86-91

2012

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Evaluation of thermal couple impedance model of power modules for accurate die temperature estimation up to 200 °C

Japanese Journal of Applied Physics, 2022-05, Vol.61 (SC), p.SC1082

2022

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Adaptive Outlier Detection for Power MOSFETs Based on Gaussian Process Regression

2022 IEEE Applied Power Electronics Conference and Exposition (APEC), 2022, p.1709-1714

2022

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EcoFlex-HDP: High-Speed and Low-Power and Programmable Hyperdimensional-Computing Platform with CPU Co-Processing

2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024, p.1-6

2024

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Robust Fault-Tolerant Design Based on Checksum and On-Line Testing for Memristor Neural Network

2021 IEEE 30th Asian Test Symposium (ATS), 2021, p.25-30

2021

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Study on High-Accuracy and Low-Cost Recycled FPGA Detection

2021 IEEE International Test Conference (ITC), 2021, p.133-142

2021

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LBIST-PUF: An LBIST Scheme Towards Efficient Challenge-Response Pairs Collection and Machine-Learning Attack Tolerance Improvement

2020 IEEE 29th Asian Test Symposium (ATS), 2020, p.1-6

2020

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Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data

2022 IEEE International Test Conference (ITC), 2022, p.573-577

2022

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Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects

2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC), 2023, p.442-448

2023

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Variation-Aware Hardware Trojan Detection through Power Side-channel

2018 IEEE International Test Conference (ITC), 2018, p.1-10

2018

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Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning

2023 IEEE International Test Conference (ITC), 2023, p.132-140

2023

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Low Cost Recycled FPGA Detection Using Virtual Probe Technique

2019 IEEE International Test Conference in Asia (ITC-Asia), 2019, p.103-108

2019

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A study on statistical parameter modeling of power MOSFET model by principal component analysis

2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS), 2019, p.107-112

2019

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Parameter Extraction Procedure for Surface-Potential-Based SiC MOSFET Model

2019 IEEE 7th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), 2019, p.444-448

2019

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Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability

Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing

IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination

Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control

Device-Parameter Estimation through IDDQ Signatures

Identification and Application of Invariant Critical Paths under NBTI Degradation

Unsupervised recycled FPGA detection using exhaustive nearest neighbor residual analysis

Accelerating Machine Learning-Based Memristor Compact Modeling Using Sparse Gaussian Process

Gaussian process-based device model toward a unified current model across room to cryogenic temperatures

Dominant Model-Parameter Determination for the Analysis of Current Imbalance Across Paralleled Power Transistors

Analog Memcapacitor by Ferroelectric Capacitor and Its Application to Spiking Neuromorphic System

A Bayesian-based process parameter estimation using IDDQ current signature

Evaluation of thermal couple impedance model of power modules for accurate die temperature estimation up to 200 °C

Adaptive Outlier Detection for Power MOSFETs Based on Gaussian Process Regression

EcoFlex-HDP: High-Speed and Low-Power and Programmable Hyperdimensional-Computing Platform with CPU Co-Processing

Robust Fault-Tolerant Design Based on Checksum and On-Line Testing for Memristor Neural Network

Study on High-Accuracy and Low-Cost Recycled FPGA Detection

LBIST-PUF: An LBIST Scheme Towards Efficient Challenge-Response Pairs Collection and Machine-Learning Attack Tolerance Improvement

Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data

Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects

Variation-Aware Hardware Trojan Detection through Power Side-channel

Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning

Low Cost Recycled FPGA Detection Using Virtual Probe Technique

A study on statistical parameter modeling of power MOSFET model by principal component analysis

Parameter Extraction Procedure for Surface-Potential-Based SiC MOSFET Model

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