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DL Michael H. Perrott Speaks on System-Level Simulation of Time-Based Circuits and Digital PLLs at SSCS Lehigh Valley [Chapters]

IEEE solid state circuits magazine, 2014-03, Vol.6 (1), p.63-66

2014

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A single-slope 80MS/s ADC using Two-Step Time-to-Digital Conversion

2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, p.1125-1128

2009

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Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm

Annual ACM IEEE Design Automation Conference: Proceedings of the 40th conference on Design automation; 02-06 June 2003, 2003, p.526-531

2003

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Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits

Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324), 2002, p.498-503

Perrott, M.H.

2002

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An efficient high-resolution 11-bit noise-shaping multipath gated ring oscillator TDC

2008 IEEE Symposium on VLSI Circuits, 2008, p.82-83

2008

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A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.340-617

2008

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A VCO-based analog-to-digital converter with second-order Sigma-Delta noise shaping

2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, p.3130-3133

2009

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A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With Frequency Stability and Integrated Jitter

IEEE journal of solid-state circuits, 2013-01, Vol.48 (1), p.276-291

2013

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A 27 mW CMOS fractional-N synthesizer/modulator IC

1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers, 1997, Vol.40, p.366-367

1997

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A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With $< \pm \hbox{0.5-ppm}$ Frequency Stability and $< \hbox{1-ps}$ Integrated Jitter

IEEE journal of solid-state circuits, 2013-01, Vol.48 (1), p.276-291

2013

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A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With < plus or minus hbox 0.5 - ppm Frequency Stability and < hbox 1 - ps Integrated Jitter

IEEE journal of solid-state circuits, 2013-01, Vol.48 (1), p.276-291

2013

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A fractional- N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2003-11, Vol.50 (11), p.839-849

2003

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Behavioral simulation of fractional-N frequency synthesizers and other PLL circuits

IEEE design & test of computers, 2002-07, Vol.19 (4), p.74-83

Perrott, M.H.

2002

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Oversampled ADC Using VCO‐Based Quantizers

Multi‐Mode/Multi‐Band RF Transceivers for Wireless Communications, 2010, p.247-277

2010

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Baroreflex gain: characterization using autoregressive moving average analysis

American journal of physiology. Heart and circulatory physiology, 1996-04, Vol.270 (4), p.H1240-H1249

1996

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A > 89% efficient LED driver with 0.5V supply voltage for applications requiring low average current

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2013, p.273-276

2013

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A low noise programmable clock multiplier based on a pulse injection-locked oscillator with a highly-digital tuning loop

2008 IEEE Radio Frequency Integrated Circuits Symposium, 2008, p.423-426

2008

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A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator

2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010, p.244-245

2010

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A modeling approach for capital sigma - Delta fractional-N frequency synthesizers allowing straightforward noise analysis

IEEE journal of solid-state circuits, 2002-08, Vol.37 (8), p.1028-1038

2002

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Bandwidth extension of low noise fractional-N synthesizers

2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers, 2005, p.211-214

2005

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A time domain approach for the fluctuation analysis of heart rate related to instantaneous lung volume

IEEE transactions on biomedical engineering, 1993-01, Vol.40 (1), p.74-81

1993

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A Delay-Locked Loop using a Synthesizer-based Phase Shifter for 3.2 Gb/s Chip-to-Chip Communication

2006 Proceedings of the 32nd European Solid-State Circuits Conference, 2006, p.460-463

2006

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Chapter 12 - Time-to-Digital Conversion for Digital Frequency Synthesizers

Advances in Analog and RF IC Design for Wireless Communication Systems, 2013, p.271-293

Perrott, Michael H.

2013

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Time-to-Digital Conversion for Digital Frequency Synthesizers

Advances in Analog and RF IC Design for Wireless Communication Systems, 2013, p.271-293

Perrott, Michael

2013

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A 10-bit 20MHz 38mW 950MHz CT ΣΔ ADC with a 5-bit noise-shaping VCO-based quantizer and DEM circuit in 0.13u cmos

2007 IEEE Symposium on VLSI Circuits, 2007, p.246-247

2007

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DL Michael H. Perrott Speaks on System-Level Simulation of Time-Based Circuits and Digital PLLs at SSCS Lehigh Valley [Chapters]

A single-slope 80MS/s ADC using Two-Step Time-to-Digital Conversion

Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm

Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits

An efficient high-resolution 11-bit noise-shaping multipath gated ring oscillator TDC

A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation

A VCO-based analog-to-digital converter with second-order Sigma-Delta noise shaping

A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With Frequency Stability and Integrated Jitter

A 27 mW CMOS fractional-N synthesizer/modulator IC

A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With $< \pm \hbox{0.5-ppm}$ Frequency Stability and $< \hbox{1-ps}$ Integrated Jitter

A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With < plus or minus hbox 0.5 - ppm Frequency Stability and < hbox 1 - ps Integrated Jitter

A fractional- N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise

Behavioral simulation of fractional-N frequency synthesizers and other PLL circuits

Oversampled ADC Using VCO‐Based Quantizers

Baroreflex gain: characterization using autoregressive moving average analysis

A > 89% efficient LED driver with 0.5V supply voltage for applications requiring low average current

A low noise programmable clock multiplier based on a pulse injection-locked oscillator with a highly-digital tuning loop

A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator

A modeling approach for capital sigma - Delta fractional-N frequency synthesizers allowing straightforward noise analysis

Bandwidth extension of low noise fractional-N synthesizers

A time domain approach for the fluctuation analysis of heart rate related to instantaneous lung volume

A Delay-Locked Loop using a Synthesizer-based Phase Shifter for 3.2 Gb/s Chip-to-Chip Communication

Chapter 12 - Time-to-Digital Conversion for Digital Frequency Synthesizers

Time-to-Digital Conversion for Digital Frequency Synthesizers

A 10-bit 20MHz 38mW 950MHz CT ΣΔ ADC with a 5-bit noise-shaping VCO-based quantizer and DEM circuit in 0.13u cmos

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