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Tunnel field-effect transistor charge-trapping memory with steep subthreshold slope and large memory window

Japanese Journal of Applied Physics, 2018-04, Vol.57 (4S), p.4

2018

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Development of Eccentric Spin Coating of Polymer Liner for Low-Temperature TSV Technology With Ultra-Fine Diameter

IEEE electron device letters, 2019-01, Vol.40 (1), p.95-98

2019

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Development of Si neural probe module with adjustable gain amplifier for neuronal signal recording

Transactions of Japanese Society for Medical and Biological Engineering, 2014, Vol.52(Supplement), pp.O-377-O-378

2014

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Development of Chip-surface Stimulus Electrode Array for Fully-implantable Subretinal Prosthesis Chip

Transactions of Japanese Society for Medical and Biological Engineering, 2014, Vol.52(Supplement), pp.O-253-O-254

2014

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Multichip thinning technology with temporary bonding for multichip-to-wafer 3D integration

Japanese Journal of Applied Physics, 2020-02, Vol.59 (SB), p.SBBA04

2020

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Reconfigured-Wafer-to-Wafer 3-D Integration Using Parallel Self-Assembly of Chips With Cu-SnAg Microbumps and a Nonconductive Film

IEEE transactions on electron devices, 2014-02, Vol.61 (2), p.533-539

2014

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An Electronic Microsaccade Circuit with Charge-Balanced Stimulation and Flicker Vision Prevention for an Artificial Eyeball System

Electronics (Basel), 2023-07, Vol.12 (13), p.2836

2023

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Development of Si neural probe with piezoresistive force sensor for minimally invasive and precise monitoring of insertion forces

Japanese Journal of Applied Physics, 2017-04, Vol.56 (4S), p.4-04CM04

2017

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Evaluation of insertion characteristics of less invasive Si optoneural probe with embedded optical fiber

Japanese Journal of Applied Physics, 2017-04, Vol.56 (4S), p.4-04CM08

2017

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Significant Die-Shift Reduction and μLED Integration Based on Die-First Fan-Out Wafer-Level Packaging for Flexible Hybrid Electronics

IEEE transactions on components, packaging, and manufacturing technology (2011), 2020-08, Vol.10 (8), p.1419-1422

2020

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High-Thermoresistant Temporary Bonding Technology for Multichip-to-Wafer 3-D Integration With Via-Last TSVs

IEEE transactions on components, packaging, and manufacturing technology (2011), 2019-01, Vol.9 (1), p.181-188

2019

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Charge-Trap-Free Polymer-Liner Through-Silicon Vias for Reliability Improvement of 3D ICs

2018 IEEE International Interconnect Technology Conference (IITC), 2018, p.135-137

2018

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Mechanical and Electrical Characterization of FOWLP-Based Flexible Hybrid Electronics (FHE) for Biomedical Sensor Application

2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019, p.264-269

2019

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On‐wafer thermomechanical characterization of a thin film polyimide formed by vapor deposition polymerization for through‐silicon via applications: Comparison to plasma‐enhanced chemical vapor deposition SiO 2

Journal of polymer science (2020), 2020-08, Vol.58 (16), p.2248-2258

2020

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Study of Insertion Characteristics of Si Neural Probe with Sharpened Tip for Minimally Invasive Insertion to Brain

Japanese Journal of Applied Physics, 2013-04, Vol.52 (4), p.04CL04-04CL04-5

2013

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Development of highly-reliable microbump bonding technology using self-assembly of NCF-covered KGDs and multi-layer 3D stacking challenges

2015 IEEE 65th Electronic Components and Technology Conference (ECTC), 2015, p.336-341

2015

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Development of Si opto neural probe with embedded optical fiber enabling layer-by-layer optical stimulation in the brain

Transactions of Japanese Society for Medical and Biological Engineering, 2017, Vol.55Annual(3AM-Abstract), pp.191-191

2017

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Development of Vertically-Stacked Multi-Shank Si Neural Probe Array with Sharpened Tip for 3-Dimensional Neural Recording

Transactions of Japanese Society for Medical and Biological Engineering, 2017, Vol.55Annual(3AM-Abstract), pp.189-189

2017

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Negative-Thermal-Expansion Gate Electrode to Introduce Tensile Strain into the Channel of MOSFETs for Mobility Enhancement

2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2023, p.1-3

2023

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Developing a Low-Temperature Flip-Chip Bonding Technology with In/Au Microbumps to Suppress the Thermal Load on Spintronics Devices

2022 IEEE International Interconnect Technology Conference (IITC), 2022, p.82-84

2022

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FOWLP-based Flexible Hybrid Electronics I: Photobiomodulation Device Fabrication on Hydrogel Substrate Using RDL-first Approach

2023 IEEE CPMT Symposium Japan (ICSJ), 2023, p.45-48

2023

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FOWLP-Based Flexible Hybrid Electronics II: Heterogeneous Integration Technology of Micro-LEDs on 3D-IC for Smart Skin Display

2023 IEEE CPMT Symposium Japan (ICSJ), 2023, p.49-52

2023

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Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC

2015 International 3D Systems Integration Conference (3DIC), 2015, p.TS8.26.1-TS8.26.4

2015

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Development of Manganese Nitride Resistor with Near-Zero Temperature-Coefficient of Resistance to Achieve High-Thermal-Stability ICs

2021 IEEE International Interconnect Technology Conference (IITC), 2021, p.1-3

2021

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Bendability Enhancement and Miniaturization of Through-X Via (TXV) Based on Flexible FOWLP with Tiny Cu Pillar Assembly

2024 IEEE 74th Electronic Components and Technology Conference (ECTC), 2024, p.849-854

2024

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Tunnel field-effect transistor charge-trapping memory with steep subthreshold slope and large memory window

Development of Eccentric Spin Coating of Polymer Liner for Low-Temperature TSV Technology With Ultra-Fine Diameter

Development of Si neural probe module with adjustable gain amplifier for neuronal signal recording

Development of Chip-surface Stimulus Electrode Array for Fully-implantable Subretinal Prosthesis Chip

Multichip thinning technology with temporary bonding for multichip-to-wafer 3D integration

Reconfigured-Wafer-to-Wafer 3-D Integration Using Parallel Self-Assembly of Chips With Cu-SnAg Microbumps and a Nonconductive Film

An Electronic Microsaccade Circuit with Charge-Balanced Stimulation and Flicker Vision Prevention for an Artificial Eyeball System

Development of Si neural probe with piezoresistive force sensor for minimally invasive and precise monitoring of insertion forces

Evaluation of insertion characteristics of less invasive Si optoneural probe with embedded optical fiber

Significant Die-Shift Reduction and μLED Integration Based on Die-First Fan-Out Wafer-Level Packaging for Flexible Hybrid Electronics

High-Thermoresistant Temporary Bonding Technology for Multichip-to-Wafer 3-D Integration With Via-Last TSVs

Charge-Trap-Free Polymer-Liner Through-Silicon Vias for Reliability Improvement of 3D ICs

Mechanical and Electrical Characterization of FOWLP-Based Flexible Hybrid Electronics (FHE) for Biomedical Sensor Application

On‐wafer thermomechanical characterization of a thin film polyimide formed by vapor deposition polymerization for through‐silicon via applications: Comparison to plasma‐enhanced chemical vapor deposition SiO 2

Study of Insertion Characteristics of Si Neural Probe with Sharpened Tip for Minimally Invasive Insertion to Brain

Development of highly-reliable microbump bonding technology using self-assembly of NCF-covered KGDs and multi-layer 3D stacking challenges

Development of Si opto neural probe with embedded optical fiber enabling layer-by-layer optical stimulation in the brain

Development of Vertically-Stacked Multi-Shank Si Neural Probe Array with Sharpened Tip for 3-Dimensional Neural Recording

Negative-Thermal-Expansion Gate Electrode to Introduce Tensile Strain into the Channel of MOSFETs for Mobility Enhancement

Developing a Low-Temperature Flip-Chip Bonding Technology with In/Au Microbumps to Suppress the Thermal Load on Spintronics Devices

FOWLP-based Flexible Hybrid Electronics I: Photobiomodulation Device Fabrication on Hydrogel Substrate Using RDL-first Approach

FOWLP-Based Flexible Hybrid Electronics II: Heterogeneous Integration Technology of Micro-LEDs on 3D-IC for Smart Skin Display

Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC

Development of Manganese Nitride Resistor with Near-Zero Temperature-Coefficient of Resistance to Achieve High-Thermal-Stability ICs

Bendability Enhancement and Miniaturization of Through-X Via (TXV) Based on Flexible FOWLP with Tiny Cu Pillar Assembly

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