UB Paderborn / Katalog / Suche / in CDI

Sortiert nach

Einfacher Volltextzugriff von (fast) überall

Installieren Sie die LibKey Nomad-Browsererweiterung und erhalten Sie von vielen Webseiten einfachen Zugriff auf lizenzierte Volltexte oder Open Access Publikationen. Mehr erfahren...

A gain reconfigurable time difference amplifier with self-adaptive linearity control

Analog integrated circuits and signal processing, 2021-05, Vol.107 (2), p.435-449

2021

Volltextzugriff (PDF)

ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors

2023 IEEE 41st International Conference on Computer Design (ICCD), 2023, p.54-61

2023

Volltextzugriff (PDF)

AdaS: A Fast and Energy-Efficient CNN Accelerator Exploiting Bit-Sparsity

2023 60th ACM/IEEE Design Automation Conference (DAC), 2023, p.1-6

2023

Volltextzugriff (PDF)

Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs

IEEE transactions on computers, 2016-01, Vol.65 (1), p.122-135

2016

Volltextzugriff (PDF)

A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-07, Vol.35 (7), p.1192-1205

2016

Volltextzugriff (PDF)

Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU

IEEE transactions on very large scale integration (VLSI) systems, 2017-02, Vol.25 (2), p.520-533

2017

Volltextzugriff (PDF)

Sneak-path based test and diagnosis for 1R RRAM crossbar using voltage bias technique

2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 2017, p.1-6

2017

Volltextzugriff (PDF)

AXNet: approximate computing using an end-to-end trainable neural network

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2018, p.1-8

2018

Volltextzugriff (PDF)

On quality trade-off control for approximate computing using iterative training

2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 2017, p.1-6

2017

Volltextzugriff (PDF)

Compiler assisted dynamic register file in GPGPU

International Symposium on Low Power Electronics and Design (ISLPED), 2013, p.3-8

2013

Volltextzugriff (PDF)

Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs

2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2016, p.1-12

2016

Volltextzugriff (PDF)

A wideband simplified transformer-based VCO with digital amplitude calibration

2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017, p.787-790

2017

Volltextzugriff (PDF)

3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-01, p.1-1

2024

Volltextzugriff (PDF)

CGSharing: Efficient content sharing in GPU-based cloud gaming

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2015, p.171-176

2015

Volltextzugriff (PDF)

E 2 -VOR: An End-to-End En/Decoder Architecture for Efficient Video Object Recognition

ACM transactions on design automation of electronic systems, 2023-01, Vol.28 (1), p.1-21

2023

Volltextzugriff (PDF)

E2-VOR: An End-to-End En/Decoder Architecture for Efficient Video Object Recognition

ACM transactions on design automation of electronic systems, 2023-01, Vol.28 (1), p.1-21, Article 10

2023

Volltextzugriff (PDF)

Bank stealing for conflict mitigation in GPGPU Register File

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2015, p.55-60

2015

Volltextzugriff (PDF)

A novel vehicle collision detection system: Integrating audio-visual fusion for enhanced performance

Expert systems with applications, 2024-09, Vol.249, p.123828, Article 123828

2024

Volltextzugriff (PDF)

A Comprehensive Dataflow-Mapping Optimization for Fully-Pipelined Execution in Spatial Programmable Architecture

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-06, p.1-1

2024

Volltextzugriff (PDF)

Jump test for metallic CNTs in CNFET-based SRAM

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, p.1-6

2015

Volltextzugriff (PDF)

On diagnosable and tunable 3D clock network design for lifetime reliability enhancement

2015 IEEE International Test Conference (ITC), 2015, p.1-10

2015

Volltextzugriff (PDF)

SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 2024, p.225-230

2024

Volltextzugriff (PDF)

Bridge-NDP: Achieving Efficient Communication-Computation Overlap in near Data Processing with Bridge Architecture

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 2024, p.460-465

2024

Volltextzugriff (PDF)

DRQ: dynamic region-based quantization for deep neural network acceleration

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020, p.1010-1021

2020

Volltextzugriff (PDF)

Janus: A Flexible Processing-in-Memory Graph Accelerator Towards Sparsity

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-05, p.1-1

2024

Volltextzugriff (PDF)

26 – 50 von 159

Menü

Weitere Dienste

Einstellungen

A gain reconfigurable time difference amplifier with self-adaptive linearity control

ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors

AdaS: A Fast and Energy-Efficient CNN Accelerator Exploiting Bit-Sparsity

Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs

A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs

Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU

Sneak-path based test and diagnosis for 1R RRAM crossbar using voltage bias technique

AXNet: approximate computing using an end-to-end trainable neural network

On quality trade-off control for approximate computing using iterative training

Compiler assisted dynamic register file in GPGPU

Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs

A wideband simplified transformer-based VCO with digital amplitude calibration

3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator

CGSharing: Efficient content sharing in GPU-based cloud gaming

E 2 -VOR: An End-to-End En/Decoder Architecture for Efficient Video Object Recognition

E2-VOR: An End-to-End En/Decoder Architecture for Efficient Video Object Recognition

Bank stealing for conflict mitigation in GPGPU Register File

A novel vehicle collision detection system: Integrating audio-visual fusion for enhanced performance

A Comprehensive Dataflow-Mapping Optimization for Fully-Pipelined Execution in Spatial Programmable Architecture

Jump test for metallic CNTs in CNFET-based SRAM

On diagnosable and tunable 3D clock network design for lifetime reliability enhancement

SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration

Bridge-NDP: Achieving Efficient Communication-Computation Overlap in near Data Processing with Bridge Architecture

DRQ: dynamic region-based quantization for deep neural network acceleration

Janus: A Flexible Processing-in-Memory Graph Accelerator Towards Sparsity

Suchergebnisse filtern