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Capacitive coupling and quantized feedback applied to conventional CMOS technology

IEEE journal of solid-state circuits, 1997-03, Vol.32 (3), p.419-427

1997

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Phantom mode signaling in VLSI systems

Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001, 2001, p.88-100

Gabara, T.

2001

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Digitally adjustable resistors in CMOS for high-performance applications

IEEE journal of solid-state circuits, 1992-08, Vol.27 (8), p.1176-1185

1992

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Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers

IEEE journal of solid-state circuits, 1997-03, Vol.32 (3), p.407-418

1997

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Dynamic structure and aqueous accessibility of poly( p-phenylene terephthalamide) crystallites

Polymer (Guilford), 1994-01, Vol.35 (6), p.1123-1131

1994

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Mise en évidence de l'activité phosphatasique acide en microscopie électronique dans les cellules du méristéme radiculairse d’Alluim cepa

Acta Societatis Botanicorum Poloniae, 2015, Vol.37 (2), p.197-200

2015

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Méthode simple pour préparation des méristèmes radiculaires permettant le détection cytochimique de certaines hydrolases

Acta Societatis Botanicorum Poloniae, 2015, Vol.32 (4), p.651-654

2015

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150/30 Mb/s CMOS non-oversampled clock and data recovery circuits with instantaneous locking and jitter rejection

Proceedings ISSCC '95 - International Solid-State Circuits Conference, 1995, p.44-45

1995

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Metastability of CMOS master/slave flip-flops

Proceedings of the IEEE 1991 Custom Integrated Circuits Conference, 1991, p.29.4/1-29.4/6

1991

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Metastability of CMOS master/slave flip-flops

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 1992-10, Vol.39 (10), p.734-740

1992

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A generic system simulator (GENESYS) for ASIC technology and architecture beyond 2001

Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit, 1996, p.193-196

1996

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LOW COST, LOW POWER DIGITAL OPTICAL RECEIVER MODULE FOR 50 Mb/s PASSIVE OPTICAL NETWORK

International journal of high speed electronics, 1996-12, Vol.7 (4), p.471-489

1996

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Low power CMOS burst-mode laser driver for full service access network application

Technical Digest. CLEO/Pacific Rim '99. Pacific Rim Conference on Lasers and Electro-Optics (Cat. No.99TH8464), 1999, Vol.2, p.519-520 vol.2

1999

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Trends in silicon-on-silicon multichip modules

IEEE design & test of computers, 1993-12, Vol.10 (4), p.8-17

1993

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Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC's with substrate-triggering technique

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334), 1997, p.287-290

1997

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An intrinsic area-array pad router for ICs

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334), 1997, p.265-269

1997

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Digital components for built-in self-test of analog circuits

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334), 1997, p.47-51

1997

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ASIC design for monobit receiver

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334), 1997, p.142-146

1997

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Tradeoffs and design of an ultra low power UHF transceiver integrated in a standard digital CMOS process

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514), 2000, p.273-278

2000

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Boundary scan access of built-in self-test for field programmable gate arrays

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334), 1997, p.57-61

1997

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Design of an ASIC architecture for high speed fractal image compression

Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit, 1996, p.223-226

1996

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Noise-aware power optimization for on-chip interconnect

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514), 2000, p.108-113

2000

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Design issues for flip-chip ICs in multilayer packages

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334), 1997, p.259-264

Frye, R.C.

1997

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A 55 MBaud single chip complex adaptive transversal equalizer for digital wireless communication systems

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334), 1997, p.151-154

1997

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Ultrastructure of rabbit spermatozoa after treatment with lysolecithin and in the presence of hamster somatic cells

Experimental biology and medicine (Maywood, N.J.), 1973-09, Vol.143 (4), p.1120-1124

1973

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Capacitive coupling and quantized feedback applied to conventional CMOS technology

Phantom mode signaling in VLSI systems

Digitally adjustable resistors in CMOS for high-performance applications

Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers

Dynamic structure and aqueous accessibility of poly( p-phenylene terephthalamide) crystallites

Mise en évidence de l'activité phosphatasique acide en microscopie électronique dans les cellules du méristéme radiculairse d’Alluim cepa

Méthode simple pour préparation des méristèmes radiculaires permettant le détection cytochimique de certaines hydrolases

150/30 Mb/s CMOS non-oversampled clock and data recovery circuits with instantaneous locking and jitter rejection

Metastability of CMOS master/slave flip-flops

Metastability of CMOS master/slave flip-flops

A generic system simulator (GENESYS) for ASIC technology and architecture beyond 2001

LOW COST, LOW POWER DIGITAL OPTICAL RECEIVER MODULE FOR 50 Mb/s PASSIVE OPTICAL NETWORK

Low power CMOS burst-mode laser driver for full service access network application

Trends in silicon-on-silicon multichip modules

Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC's with substrate-triggering technique

An intrinsic area-array pad router for ICs

Digital components for built-in self-test of analog circuits

ASIC design for monobit receiver

Tradeoffs and design of an ultra low power UHF transceiver integrated in a standard digital CMOS process

Boundary scan access of built-in self-test for field programmable gate arrays

Design of an ASIC architecture for high speed fractal image compression

Noise-aware power optimization for on-chip interconnect

Design issues for flip-chip ICs in multilayer packages

A 55 MBaud single chip complex adaptive transversal equalizer for digital wireless communication systems

Ultrastructure of rabbit spermatozoa after treatment with lysolecithin and in the presence of hamster somatic cells

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