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In-Memory Hamming Error-Correcting Code in Memristor Crossbar

IEEE transactions on electron devices, 2022-07, Vol.69 (7), p.3700-3707

2022

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A low-power pulse position modulation transceiver

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, p.1614-1617

2015

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Design and Analysis of Asynchronous Sampling Duty Cycle Corrector

Electronics (Basel), 2021-11, Vol.10 (21), p.2594

2021

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A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, p.2389-2392

2015

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A crossbar resistance switching memory readout scheme with sneak current cancellation based on a two-port current-mode sensing

Nanotechnology, 2016-12, Vol.27 (48), p.485201-485201

2016

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An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET

IEEE journal of solid-state circuits, 2022-01, Vol.57 (1), p.140-152

2022

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A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC), 2014, p.447-450

2014

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A High-Frequency and Low-Jitter DLL with Quadrature Error and Duty Cycle Corrections Based on Asynchronous Sampling

IEEE solid-state circuits letters, 2023-01, Vol.6, p.1-1

2023

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BAG2: A process-portable framework for generator-based AMS circuit design

2018 IEEE Custom Integrated Circuits Conference (CICC), 2018, p.1-8

2018

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A Variation-Tolerant, Sneak-Current-Compensated Readout Scheme for Cross-Point Memory Based on Two-Port Sensing Technique

IEEE transactions on circuits and systems. II, Express briefs, 2018-12, Vol.65 (12), p.1839-1843

2018

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A power‐efficient 600‐mV pp voltage‐mode driver with independently matched pull‐up and pull‐down impedances

International journal of circuit theory and applications, 2015-12, Vol.43 (12), p.2057-2071

2015

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A power-efficient 600-mV sub(pp) voltage-mode driver with independently matched pull-up and pull-down impedances

International journal of circuit theory and applications, 2015-12, Vol.43 (12), p.2057-2071

2015

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A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET

IEEE journal of solid-state circuits, 2019-07, Vol.54 (7), p.1993-2008

2019

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A Novel Stateful Logic Device and Circuit for In‐Memory Parity Programming in Crossbar Memory

Advanced electronic materials, 2020-12, Vol.6 (12), p.n/a

2020

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A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2016-12, Vol.63 (12), p.1106-1110

2016

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A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

Electronics (Basel), 2021-01, Vol.10 (1), p.68

2021

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A 256Gbps Microring-Based WDM Transceiver with Error-Free Wide Temperature Operation for Co-Packaged Optical I/O Chiplets

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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Comprehensive Writing Margin Analysis and its Application to Stacked one Diode-One Memory Device for High-Density Crossbar Resistance Switching Random Access Memory

Advanced electronic materials, 2016-10, Vol.2 (10), p.n/a

2016

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A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance

IEEE journal of solid-state circuits, 2019-10, Vol.54 (10), p.2786-2801

2019

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Design of a Transceiver Transmitting Power, Clock, and Data over a Single Optical Fiber for Future Automotive Network System

Journal of semiconductor technology and science, 2017, Vol.17 (1), p.48-55

2017

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A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2018-04, Vol.65 (4), p.436-440

2018

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A power-efficient 600-mVpp voltage-mode driver with independently matched pull-up and pull-down impedances

International journal of circuit theory and applications, 2015-12, Vol.43 (12), p.2057-2071

2015

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TeraPHY: An O-Band WDM Electro-Optic Platform for Low Power, Terabit/s Optical I/O

2020 IEEE Symposium on VLSI Technology, 2020, p.1-2

2020

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4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.58-60

2021

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A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS

2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2016, p.241-244

2016

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In-Memory Hamming Error-Correcting Code in Memristor Crossbar

A low-power pulse position modulation transceiver

Design and Analysis of Asynchronous Sampling Duty Cycle Corrector

A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS

A crossbar resistance switching memory readout scheme with sneak current cancellation based on a two-port current-mode sensing

An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET

A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line

A High-Frequency and Low-Jitter DLL with Quadrature Error and Duty Cycle Corrections Based on Asynchronous Sampling

BAG2: A process-portable framework for generator-based AMS circuit design

A Variation-Tolerant, Sneak-Current-Compensated Readout Scheme for Cross-Point Memory Based on Two-Port Sensing Technique

A power‐efficient 600‐mV pp voltage‐mode driver with independently matched pull‐up and pull‐down impedances

A power-efficient 600-mV sub(pp) voltage-mode driver with independently matched pull-up and pull-down impedances

A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET

A Novel Stateful Logic Device and Circuit for In‐Memory Parity Programming in Crossbar Memory

A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS

A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

A 256Gbps Microring-Based WDM Transceiver with Error-Free Wide Temperature Operation for Co-Packaged Optical I/O Chiplets

Comprehensive Writing Margin Analysis and its Application to Stacked one Diode-One Memory Device for High-Density Crossbar Resistance Switching Random Access Memory

A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance

Design of a Transceiver Transmitting Power, Clock, and Data over a Single Optical Fiber for Future Automotive Network System

A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS

A power-efficient 600-mVpp voltage-mode driver with independently matched pull-up and pull-down impedances

TeraPHY: An O-Band WDM Electro-Optic Platform for Low Power, Terabit/s Optical I/O

4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET

A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS

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