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Impact of SOI Substrate on the Radiation Response of UltraThin Transistors Down to the 20 nm Node

IEEE transactions on nuclear science, 2013-08, Vol.60 (4), p.2583-2589

2013

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Comprehensive Evaluation of Junctionless and Inversion-Mode Nanowire MOSFETs Performance at High Temperatures

IEEE journal of the Electron Devices Society, 2024, Vol.12, p.682-691

2024

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High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

IEEE journal of the Electron Devices Society, 2023-01, Vol.11, p.1-1

2023

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Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

IEEE transactions on electron devices, 2013-02, Vol.60 (2), p.727-732

2013

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Carrier-Mobility Enhancement via Strain Engineering in Future Thin-Body MOSFETs

IEEE electron device letters, 2012-03, Vol.33 (3), p.318-320

2012

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Transient Radiation Response of Single- and Multiple-Gate FD SOI Transistors

IEEE transactions on nuclear science, 2007-12, Vol.54 (6), p.2355-2362

2007

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BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

IEEE transactions on electron devices, 2012-08, Vol.59 (8), p.2019-2026

2012

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GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current

IEEE electron device letters, 2010-03, Vol.31 (3), p.234-236

2010

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Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC), 2021, p.223-226

2021

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Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Microelectronic engineering, 2017-06, Vol.178, p.17-20

2017

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Arsenic-Segregated Rare-Earth Silicide Junctions: Reduction of Schottky Barrier and Integration in Metallic n-MOSFETs on SOI

IEEE electron device letters, 2009-12, Vol.30 (12), p.1266-1268

2009

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3D analytical modelling of subthreshold characteristics in vertical Multiple-gate FinFET transistors

Solid-state electronics, 2011-11, Vol.65-66, p.94-102

2011

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Bias-Engineered Mobility in Advanced FD-SOI MOSFETs

IEEE electron device letters, 2013-07, Vol.34 (7), p.840-842

2013

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High-Performance Ultrathin Body c-SiGe Channel FDSOI pMOSFETs Featuring SiGe Source and Drain: Vth Tuning, Variability, Access Resistance, and Mobility Issues

IEEE transactions on electron devices, 2013-05, Vol.60 (5), p.1568-1574

2013

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Multibranch Mobility Analysis for the Characterization of FDSOI Transistors

IEEE electron device letters, 2012-08, Vol.33 (8), p.1102-1104

2012

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SOI 1T-DRAM cells with variable channel length and thickness: Experimental comparison of programming mechanisms

Solid-state electronics, 2011-11, Vol.65-66, p.256-262

2011

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Experimental investigation of ESD design window for fully depleted SOI N-MOSFETs

Microelectronic engineering, 2011-07, Vol.88 (7), p.1276-1279

2011

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Multi-Channel Field-Effect Transistor (MCFET)-Part I: Electrical Performance and Current Gain Analysis

IEEE transactions on electron devices, 2009-06, Vol.56 (6), p.1243-1251

2009

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Opportunities brought by sequential 3D CoolCube™ integration

2016 46th European Solid-State Device Research Conference (ESSDERC), 2016, p.226-229

2016

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Fully Depleted Strained Silicon-on-Insulator p-MOSFETs With Recessed and Embedded Silicon-Germanium Source/Drain

IEEE electron device letters, 2010-10, Vol.31 (10), p.1074-1076

2010

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On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells : CHARACTERIZATION OF NANO CMOS VARIABIALITY BY SIMULATION AND MEASUREMENTS

IEEE transactions on electron devices, 2011, Vol.58 (8), p.2326-2336

2011

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Study of substrate orientations impact on Ultra Thin Buried Oxide (UTBOX) FDSOI High-K Metal gate technology performances

Solid-state electronics, 2013-12, Vol.90, p.143-148

2013

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4-port RF performance assessment and compact modeling of UTBB-FDSOI transistors

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015, p.355-358

2015

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Multi-Channel Field-Effect Transistor (MCFET)-Part II: Analysis of Gate Stack and Series Resistance Influence on the MCFET Performance

IEEE transactions on electron devices, 2009-06, Vol.56 (6), p.1252-1261

2009

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Integration of diamond in fully-depleted silicon-on-insulator technology as buried insulator: A theoretical analysis

Diamond and related materials, 2008-07, Vol.17 (7), p.1248-1251

2008

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Impact of SOI Substrate on the Radiation Response of UltraThin Transistors Down to the 20 nm Node

Comprehensive Evaluation of Junctionless and Inversion-Mode Nanowire MOSFETs Performance at High Temperatures

High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

Carrier-Mobility Enhancement via Strain Engineering in Future Thin-Body MOSFETs

Transient Radiation Response of Single- and Multiple-Gate FD SOI Transistors

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Arsenic-Segregated Rare-Earth Silicide Junctions: Reduction of Schottky Barrier and Integration in Metallic n-MOSFETs on SOI

3D analytical modelling of subthreshold characteristics in vertical Multiple-gate FinFET transistors

Bias-Engineered Mobility in Advanced FD-SOI MOSFETs

High-Performance Ultrathin Body c-SiGe Channel FDSOI pMOSFETs Featuring SiGe Source and Drain: Vth Tuning, Variability, Access Resistance, and Mobility Issues

Multibranch Mobility Analysis for the Characterization of FDSOI Transistors

SOI 1T-DRAM cells with variable channel length and thickness: Experimental comparison of programming mechanisms

Experimental investigation of ESD design window for fully depleted SOI N-MOSFETs

Multi-Channel Field-Effect Transistor (MCFET)-Part I: Electrical Performance and Current Gain Analysis

Opportunities brought by sequential 3D CoolCube™ integration

Fully Depleted Strained Silicon-on-Insulator p-MOSFETs With Recessed and Embedded Silicon-Germanium Source/Drain

On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells : CHARACTERIZATION OF NANO CMOS VARIABIALITY BY SIMULATION AND MEASUREMENTS

Study of substrate orientations impact on Ultra Thin Buried Oxide (UTBOX) FDSOI High-K Metal gate technology performances

4-port RF performance assessment and compact modeling of UTBB-FDSOI transistors

Multi-Channel Field-Effect Transistor (MCFET)-Part II: Analysis of Gate Stack and Series Resistance Influence on the MCFET Performance

Integration of diamond in fully-depleted silicon-on-insulator technology as buried insulator: A theoretical analysis

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