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pH Quantification in Human Dermal Interstitial Fluid Using Ultra-Thin SOI Silicon Nanowire ISFETs and a High-Sensitivity Constant-Current Approach

Biosensors (Basel), 2023-09, Vol.13 (10), p.908

2023

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Low-temperature electrical characterization of junctionless transistors

Solid-state electronics, 2013-02, Vol.80, p.135-141

2013

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Analysis of the Electrical Parameters of SOI Junctionless Nanowire Transistors at High Temperatures

IEEE journal of the Electron Devices Society, 2021, Vol.9, p.492-499

2021

Volltextzugriff (PDF)

Less mobility degradation induced by transverse electric-field in junctionless transistors

Applied physics letters, 2014-11, Vol.105 (21)

2014

Volltextzugriff (PDF)

Integration of Ultra-Low Volume Pneumatic Microfluidics with a Three-Dimensional Electrode Network for On-Chip Biochemical Sensing

Micromachines (Basel), 2021-06, Vol.12 (7), p.762

2021

Volltextzugriff (PDF)

High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

IEEE journal of the Electron Devices Society, 2023-01, Vol.11, p.1-1

2023

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Charge Dynamics and Spin Blockade in a Hybrid Double Quantum Dot in Silicon

Physical review. X, 2015-08, Vol.5 (3), p.031024, Article 031024

2015

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Primary thermometry of a single reservoir using cyclic electron tunneling to a quantum dot

Communications physics, 2018-10, Vol.1 (1), Article 66

2018

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Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

IEEE transactions on electron devices, 2013-02, Vol.60 (2), p.727-732

2013

Volltextzugriff (PDF)

A silicon-based single-electron interferometer coupled to a fermionic sea

Physical review. B, 2018-01, Vol.97 (4), Article 045405

2018

Volltextzugriff (PDF)

Low-frequency noise behavior of junctionless transistors compared to inversion-mode transistors

Solid-state electronics, 2013-03, Vol.81, p.101-104

2013

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Process Variability-Technological Challenge and Design Issue for Nanoscale Devices

Micromachines (Basel), 2019-01, Vol.10 (1), p.6

2019

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Effects of channel width variation on electrical characteristics of tri-gate Junctionless transistors

Solid-state electronics, 2013-03, Vol.81, p.58-62

2013

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Separation of surface accumulation and bulk neutral channel in junctionless transistors

Applied physics letters, 2014-06, Vol.104 (26)

2014

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Channel-Width-Dependent Mobility Degradation in Bulk Conduction Regime of Tri-Gate Junctionless Transistors

IEEE transactions on electron devices, 2022-06, Vol.69 (6), p.3037-3041

2022

Volltextzugriff (PDF)

Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors

Microelectronic engineering, 2019-07, Vol.215, p.111005, Article 111005

2019

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Impact of Channel Length on the Operation of Junctionless Transistors With Substrate Biasing

IEEE transactions on electron devices, 2021-06, Vol.68 (6), p.3070-3073

2021

Volltextzugriff (PDF)

Controlling the Effective Channel Thickness of Junctionless Transistors by Substrate Bias

IEEE transactions on electron devices, 2020-11, Vol.67 (11), p.4736-4740

2020

Volltextzugriff (PDF)

Variability Modeling in Triple-Gate Junctionless Nanowire Transistors

IEEE transactions on electron devices, 2022-08, Vol.69 (8), p.4730-4736

2022

Volltextzugriff (PDF)

Comprehensive Evaluation of Junctionless and Inversion-Mode Nanowire MOSFETs Performance at High Temperatures

IEEE journal of the Electron Devices Society, 2024-06, p.1-1

2024

Volltextzugriff (PDF)

Pragmatic evaluation of fin height and fin width combined variation impact on the performance of junctionless transistors

Journal of computational electronics, 2022-06, Vol.21 (3), p.654-665

2022

Volltextzugriff (PDF)

Analytical Drain Current Compact Model in the Depletion Operation Region of Short-Channel Triple-Gate Junctionless Transistors

IEEE transactions on electron devices, 2017-01, Vol.64 (1), p.66-72

2017

Volltextzugriff (PDF)

On the Application of Junctionless Nanowire Transistors in Basic Analog Building Blocks

IEEE transactions on nanotechnology, 2021, Vol.20, p.234-242

2021

Volltextzugriff (PDF)

Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors

IEEE transactions on electron devices, 2016-02, Vol.63 (2), p.856-863

2016

Volltextzugriff (PDF)

Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Microelectronic engineering, 2017-06, Vol.178, p.17-20

2017

Volltextzugriff (PDF)

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pH Quantification in Human Dermal Interstitial Fluid Using Ultra-Thin SOI Silicon Nanowire ISFETs and a High-Sensitivity Constant-Current Approach

Low-temperature electrical characterization of junctionless transistors

Analysis of the Electrical Parameters of SOI Junctionless Nanowire Transistors at High Temperatures

Less mobility degradation induced by transverse electric-field in junctionless transistors

Integration of Ultra-Low Volume Pneumatic Microfluidics with a Three-Dimensional Electrode Network for On-Chip Biochemical Sensing

High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

Charge Dynamics and Spin Blockade in a Hybrid Double Quantum Dot in Silicon

Primary thermometry of a single reservoir using cyclic electron tunneling to a quantum dot

Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

A silicon-based single-electron interferometer coupled to a fermionic sea

Low-frequency noise behavior of junctionless transistors compared to inversion-mode transistors

Process Variability-Technological Challenge and Design Issue for Nanoscale Devices

Effects of channel width variation on electrical characteristics of tri-gate Junctionless transistors

Separation of surface accumulation and bulk neutral channel in junctionless transistors

Channel-Width-Dependent Mobility Degradation in Bulk Conduction Regime of Tri-Gate Junctionless Transistors

Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors

Impact of Channel Length on the Operation of Junctionless Transistors With Substrate Biasing

Controlling the Effective Channel Thickness of Junctionless Transistors by Substrate Bias

Variability Modeling in Triple-Gate Junctionless Nanowire Transistors

Comprehensive Evaluation of Junctionless and Inversion-Mode Nanowire MOSFETs Performance at High Temperatures

Pragmatic evaluation of fin height and fin width combined variation impact on the performance of junctionless transistors

Analytical Drain Current Compact Model in the Depletion Operation Region of Short-Channel Triple-Gate Junctionless Transistors

On the Application of Junctionless Nanowire Transistors in Basic Analog Building Blocks

Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors

Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

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