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Linear-Time Temporal Answer Set Programming

Theory and practice of logic programming, 2023-01, Vol.23 (1), p.2-56

2023

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Real-time efficient FPGA implementation of aes algorithm

2013 IEEE International SOC Conference, 2013, p.203-208

2013

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An optimal design of a fault tolerant reversible multiplier

2013 IEEE International SOC Conference, 2013, p.37-42

2013

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A disturb-free subthreshold 9T SRAM cell with improved performance and variation tolerance

2013 IEEE International SOC Conference, 2013, p.325-329

2013

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Latency-optimization synthesis with module selection for digital microfluidic biochips

2013 IEEE International SOC Conference, 2013, p.159-164

2013

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An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder

2013 IEEE International SOC Conference, 2013, p.98-103

2013

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PKF: A communication cost reduction schema based on Kalman filter and data prediction for Wireless Sensor Networks

2013 IEEE International SOC Conference, 2013, p.73-78

2013

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A novel approach to design a reversible shifter circuit using DNA

2013 IEEE International SOC Conference, 2013, p.256-261

2013

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Design-for-testability automation of mixed-signal integrated circuits

2013 IEEE International SOC Conference, 2013, p.244-249

Mosin, Sergey

2013

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A wide range programmable duty cycle corrector

2013 IEEE International SOC Conference, 2013, p.192-196

2013

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A robust medium access mechanism for millimeter-wave Wireless Network-on-Chip architecture

2013 IEEE International SOC Conference, 2013, p.362-367

2013

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High-performance adaption of ARM processors into Network-on-Chip architectures

2013 IEEE International SOC Conference, 2013, p.222-227

2013

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UWB receiver for breast cancer detection: Comparison between two different approaches

2013 IEEE International SOC Conference, 2013, p.55-60

2013

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A low cost method to tolerate soft errors in the NoC router control plane

2013 IEEE International SOC Conference, 2013, p.374-379

2013

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High-level TSV resource sharing and optimization for TSV based 3D IC designs

2013 IEEE International SOC Conference, 2013, p.153-158

2013

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Rapid prototyping of a portable HW/SW co-design on the virtual zynq platform using SystemC

2013 IEEE International SOC Conference, 2013, p.296-300

2013

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A formalism of the specifications for library development

2013 IEEE International SOC Conference, 2013, p.307-312

2013

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A comprehensive operand-aware dynamic clock gating scheme for low-power Domino Logic

2013 IEEE International SOC Conference, 2013, p.349-354

2013

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Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operation

2013 IEEE International SOC Conference, 2013, p.105-109

2013

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Development of advanced diagnostic functions in very high volume automotive sensor applications

2013 IEEE International SOC Conference, 2013, p.123-128

2013

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Integrated routing and channel arbitration in overlaid mesh WiNoC

2013 IEEE International SOC Conference, 2013, p.368-373

2013

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A BCH decoding architecture with mixed parallelization degrees for flash controller applications

2013 IEEE International SOC Conference, 2013, p.116-121

2013

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Quotient prediction for low power division

2013 IEEE International SOC Conference, 2013, p.273-277

2013

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SOSoC, a Linux framework for System Optimization using System on Chip

2013 IEEE International SOC Conference, 2013, p.284-289

2013

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Morpack Cube: A portable 3D heterogeneous system integration platform

2013 IEEE International SOC Conference, 2013, p.197-202

2013

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Linear-Time Temporal Answer Set Programming

Real-time efficient FPGA implementation of aes algorithm

An optimal design of a fault tolerant reversible multiplier

A disturb-free subthreshold 9T SRAM cell with improved performance and variation tolerance

Latency-optimization synthesis with module selection for digital microfluidic biochips

An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder

PKF: A communication cost reduction schema based on Kalman filter and data prediction for Wireless Sensor Networks

A novel approach to design a reversible shifter circuit using DNA

Design-for-testability automation of mixed-signal integrated circuits

A wide range programmable duty cycle corrector

A robust medium access mechanism for millimeter-wave Wireless Network-on-Chip architecture

High-performance adaption of ARM processors into Network-on-Chip architectures

UWB receiver for breast cancer detection: Comparison between two different approaches

A low cost method to tolerate soft errors in the NoC router control plane

High-level TSV resource sharing and optimization for TSV based 3D IC designs

Rapid prototyping of a portable HW/SW co-design on the virtual zynq platform using SystemC

A formalism of the specifications for library development

A comprehensive operand-aware dynamic clock gating scheme for low-power Domino Logic

Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operation

Development of advanced diagnostic functions in very high volume automotive sensor applications

Integrated routing and channel arbitration in overlaid mesh WiNoC

A BCH decoding architecture with mixed parallelization degrees for flash controller applications

Quotient prediction for low power division

SOSoC, a Linux framework for System Optimization using System on Chip

Morpack Cube: A portable 3D heterogeneous system integration platform

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