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Use of Sulfur Isotope Ratios To Determine Anthropogenic Sulfur Signals in a Grassland Ecosystem

Environmental science & technology, 1998-08, Vol.32 (15), p.2288-2291

1998

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PROBLEMS IN ANALYSIS AND TERMINOLOGY FOR INFORMATION RETRIEVAL

Journal of documentation, 1965-04, Vol.21 (4), p.287-290

1965

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A Single-Chip Optical Phased Array in a Wafer-Scale Silicon Photonics/CMOS 3D-Integration Platform

IEEE journal of solid-state circuits, 2019-11, Vol.54 (11), p.3061-3074

2019

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Coherent LiDAR With an 8,192-Element Optical Phased Array and Driving Laser

IEEE journal of selected topics in quantum electronics, 2022-09, Vol.28 (5: Lidars and Photonic Radars), p.1-8

2022

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CMOS-Compatible Optical Phased Array Powered by a Monolithically-Integrated Erbium Laser

Journal of lightwave technology, 2019-12, Vol.37 (24), p.5982-5987

2019

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Near-Field-Focusing Integrated Optical Phased Arrays

Journal of lightwave technology, 2018-12, Vol.36 (24), p.5912-5920

2018

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Long-Range LiDAR and Free-Space Data Communication With High-Performance Optical Phased Arrays

IEEE journal of selected topics in quantum electronics, 2019-09, Vol.25 (5), p.1-8

2019

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A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS

IEEE journal of solid-state circuits, 2007-12, Vol.42 (12), p.2745-2757

2007

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A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator

IEEE journal of solid-state circuits, 2019-01, Vol.54 (1), p.43-54

2019

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A two-phase approach to elicit and measure beliefs on management strategies: Fishers supportive and aware of trade-offs associated with stock enhancement

Ambio, 2020-02, Vol.49 (2), p.640-649

2020

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A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips

IEEE journal of solid-state circuits, 2002-12, Vol.37 (12), p.1804-1812

2002

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State‐wide utilization and performance of traditional and cell‐free DNA‐based prenatal testing pathways: the Victorian Perinatal Record Linkage (PeRL) study

Ultrasound in obstetrics & gynecology, 2020-08, Vol.56 (2), p.215-224

2020

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Gravitational wave alert generation infrastructure on your laptop

EPJ Web of Conferences, 2024, Vol.295, p.4022

2024

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A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation

IEEE journal of solid-state circuits, 2016-02, Vol.51 (2), p.557-567

2016

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A 2048-channel, 125μW/ch DAC Controlling a 9,216-element Optical Phased Array Coherent Solid-State LiDAR

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, p.1-2

2023

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Jitter transfer characteristics of delay-locked loops - theories and design techniques

IEEE journal of solid-state circuits, 2003-04, Vol.38 (4), p.614-621

2003

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The use of hydrous iron (III) oxides for the removal of hydrogen sulphide in aqueous systems

Water research (Oxford), 2002-02, Vol.36 (4), p.825-834

2002

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Effective properties of periodic plate-array metacylinders

Physical review. B, 2023-12, Vol.108 (21), Article 214105

2023

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A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling

IEEE journal of solid-state circuits, 2010-04, Vol.45 (4), p.889-898

2010

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Slow convergence to effective medium in finite discrete metamaterials

Physical review. B, 2016-06, Vol.93 (23), Article 235156

2016

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FDTD-Modelling of Dispersive Nonlinear Ring Resonators: Accuracy Studies and Experiments

IEEE journal of quantum electronics, 2006-12, Vol.42 (12), p.1215-1223

2006

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A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.276-278

2018

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A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013, p.466-467

2013

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A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

IEEE journal of solid-state circuits, 2004-09, Vol.39 (9), p.1553-1561

2004

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DNA self-assembled parallel computer architectures

Nanotechnology, 2004-11, Vol.15 (11), p.1688-1694

2004

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Use of Sulfur Isotope Ratios To Determine Anthropogenic Sulfur Signals in a Grassland Ecosystem

PROBLEMS IN ANALYSIS AND TERMINOLOGY FOR INFORMATION RETRIEVAL

A Single-Chip Optical Phased Array in a Wafer-Scale Silicon Photonics/CMOS 3D-Integration Platform

Coherent LiDAR With an 8,192-Element Optical Phased Array and Driving Laser

CMOS-Compatible Optical Phased Array Powered by a Monolithically-Integrated Erbium Laser

Near-Field-Focusing Integrated Optical Phased Arrays

Long-Range LiDAR and Free-Space Data Communication With High-Performance Optical Phased Arrays

A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS

A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator

A two-phase approach to elicit and measure beliefs on management strategies: Fishers supportive and aware of trade-offs associated with stock enhancement

A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips

State‐wide utilization and performance of traditional and cell‐free DNA‐based prenatal testing pathways: the Victorian Perinatal Record Linkage (PeRL) study

Gravitational wave alert generation infrastructure on your laptop

A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation

A 2048-channel, 125μW/ch DAC Controlling a 9,216-element Optical Phased Array Coherent Solid-State LiDAR

Jitter transfer characteristics of delay-locked loops - theories and design techniques

The use of hydrous iron (III) oxides for the removal of hydrogen sulphide in aqueous systems

Effective properties of periodic plate-array metacylinders

A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling

Slow convergence to effective medium in finite discrete metamaterials

FDTD-Modelling of Dispersive Nonlinear Ring Resonators: Accuracy Studies and Experiments

A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator

A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

DNA self-assembled parallel computer architectures

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