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MAPS: Mapping Concurrent Dataflow Applications to Heterogeneous MPSoCs

IEEE transactions on industrial informatics, 2013-02, Vol.9 (1), p.527-545

2013

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ConvAix: An Application-Specific Instruction-Set Processor for the Efficient Acceleration of CNNs

IEEE open journal of circuits and systems, 2021, Vol.2, p.3-15

2021

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AMAIX In-Depth: A Generic Analytical Model for Deep Learning Accelerators

International journal of parallel programming, 2022-04, Vol.50 (2), p.295-318

2022

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Accelerating Deep Learning Inference in Constrained Embedded Devices Using Hardware Loops and a Dot Product Unit

IEEE access, 2020, Vol.8, p.165913-165926

2020

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Density-Based Statistical Clustering: Enabling Sidefire Ultrasonic Traffic Sensing in Smart Cities

Journal of advanced transportation, 2018-01, Vol.2018 (2018), p.1-15

2018

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C Compilers for ASIPs: Automatic Compiler Generation with LISA

1. Aufl., 2010

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Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-06, Vol.41 (6), p.1716-1729

2022

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Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach

ACM journal on emerging technologies in computing systems, 2021-07, Vol.17 (3), p.1-26

2021

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Parameterized Posit Arithmetic Hardware Generator

2018 IEEE 36th International Conference on Computer Design (ICCD), 2018, p.334-341

2018

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A Scalable, Multimode SVD Precoding ASIC Based on the Cyclic Jacobi Method

IEEE transactions on circuits and systems. I, Regular papers, 2016-08, Vol.63 (8), p.1283-1294

2016

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Technology Transfer in computing systems: The TETRACOM approach

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, p.834-837

Leupers, Rainer

2016

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veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing

IEEE transactions on circuits and systems. I, Regular papers, 2024-09, Vol.71 (9), p.4169-4179

2024

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Efficiency Enablers of Lightweight SDR for MIMO Baseband Processing

IEEE transactions on very large scale integration (VLSI) systems, 2016-02, Vol.24 (2), p.567-577

2016

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It's Getting Hot in Here: Hardware Security Implications of Thermal Crosstalk on ReRAMs

IEEE transactions on reliability, 2024-03, p.1-15

2024

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Unified Identification of Multiple Forms of Parallelism in Embedded Applications

2015 International Conference on Parallel Architecture and Compilation (PACT), 2015, p.482-483

2015

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An Investigation on Inherent Robustness of Posit Data Representation

2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID), 2021, p.276-281

2021

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CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism

Journal of systems architecture, 2023-02, Vol.135, p.102801, Article 102801

2023

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Modelling Machine Learning Components for Mapping and Scheduling of AUTOSAR Runnables

2020 IEEE 31st International Symposium on Software Reliability Engineering (ISSRE), 2020, p.127-137

2020

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X-on-X: Distributed Parallel Virtual Platforms for Heterogeneous Systems

2022 25th Euromicro Conference on Digital System Design (DSD), 2022, p.142-148

2022

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An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration

2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, p.1-5

2019

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QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog

2021 IEEE 39th International Conference on Computer Design (ICCD), 2021, p.603-607

2021

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Flexible, Efficient Multimode MIMO Detection by Using Reconfigurable ASIP

IEEE transactions on very large scale integration (VLSI) systems, 2015-10, Vol.23 (10), p.2173-2186

2015

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Designing ML-resilient locking at register-transfer level

Proceedings of the 59th ACM/IEEE Design Automation Conference, 2022, p.769-774

2022

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NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022, p.1181-1184

2022

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ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework

2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID), 2021, p.270-275

2021

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MAPS: Mapping Concurrent Dataflow Applications to Heterogeneous MPSoCs

ConvAix: An Application-Specific Instruction-Set Processor for the Efficient Acceleration of CNNs

AMAIX In-Depth: A Generic Analytical Model for Deep Learning Accelerators

Accelerating Deep Learning Inference in Constrained Embedded Devices Using Hardware Loops and a Dot Product Unit

Density-Based Statistical Clustering: Enabling Sidefire Ultrasonic Traffic Sensing in Smart Cities

C Compilers for ASIPs: Automatic Compiler Generation with LISA

Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks

Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach

Parameterized Posit Arithmetic Hardware Generator

A Scalable, Multimode SVD Precoding ASIC Based on the Cyclic Jacobi Method

Technology Transfer in computing systems: The TETRACOM approach

veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing

Efficiency Enablers of Lightweight SDR for MIMO Baseband Processing

It's Getting Hot in Here: Hardware Security Implications of Thermal Crosstalk on ReRAMs

Unified Identification of Multiple Forms of Parallelism in Embedded Applications

An Investigation on Inherent Robustness of Posit Data Representation

CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism

Modelling Machine Learning Components for Mapping and Scheduling of AUTOSAR Runnables

X-on-X: Distributed Parallel Virtual Platforms for Heterogeneous Systems

An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration

QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog

Flexible, Efficient Multimode MIMO Detection by Using Reconfigurable ASIP

Designing ML-resilient locking at register-transfer level

NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories

ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework

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