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Circuit Level Layout Optimization of MOS Transistor for RF and Noise Performance Improvements

IEEE transactions on electron devices, 2016-12, Vol.63 (12), p.4674-4677

2016

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Device and Circuit Exploration of Multi-Nanosheet Transistor for Sub-3 nm Technology Node

Electronics (Basel), 2021-01, Vol.10 (2), p.180

2021

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Non-volatile logic-in-memory ternary content addressable memory circuit with floating gate field effect transistor

AIP advances, 2023-04, Vol.13 (4), p.045211-045211-13

2023

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Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory Devices

Micromachines (Basel), 2024-04, Vol.15 (4), p.450

2024

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Investigation of Electrothermal Behaviors of 5-nm Bulk FinFET

IEEE transactions on electron devices, 2017-12, Vol.64 (12), p.5284-5287

2017

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Logic-in-memory application of ferroelectric-based WS2-channel field-effect transistors for improved area and energy efficiency

NPJ 2D materials and applications, 2024-04, Vol.8 (1), p.29-9, Article 29

2024

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Device and Circuit Analysis of Double Gate Field Effect Transistor with Mono-Layer WS2-Channel at Sub-2 nm Technology Node

Nanomaterials (Basel, Switzerland), 2022-07, Vol.12 (13), p.2299

2022

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Self-heating and Corner Rounding Effects on Time Dependent Dielectric Breakdown of Stacked Multi-Nanosheet FETs

IEEE access, 2023-01, Vol.11, p.1-1

2023

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Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET)

IEEE access, 2023, Vol.11, p.97778-97785

2023

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Investigation on the effects of interconnect RC in 3nm technology node using Path-Finding Process Design Kit

IEEE access, 2022, Vol.10, p.1-1

2022

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Modulation of Contact Resistance of Dual‐Gated MoS2 FETs Using Fermi‐Level Pinning‐Free Antimony Semi‐Metal Contacts

Advanced science, 2023-07, Vol.10 (21), p.e2301400-n/a

2023

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Study on the Circuit Performance of Various Interconnect Metal Materials in the Latest Process Nodes

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2023, 23(4), 112, pp.215-227

2023

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Temporal Noise Analysis and Reduction Method in CMOS Image Sensor Readout Circuit

IEEE transactions on electron devices, 2009-11, Vol.56 (11), p.2489-2495

2009

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Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage

Nanomaterials (Basel, Switzerland), 2022-02, Vol.12 (4), p.591

2022

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Large-Scale Training in Neural Compact Models for Accurate and Adaptable MOSFET Simulation

IEEE journal of the Electron Devices Society, 2024, Vol.12, p.745-751

2024

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Hyper-FET's Phase-Transition-Materials Design Guidelines for Ultra-Low Power Applications at 3 nm Technology Node

Nanomaterials (Basel, Switzerland), 2022-11, Vol.12 (22), p.4096

2022

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Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test Circuits

IEEE access, 2023, Vol.11, p.70691-70697

2023

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Highly Strained Si pFinFET on SiC With Good Control of Sub-Fin Leakage and Self-Heating

IEEE electron device letters, 2014-12, Vol.35 (12), p.1191-1193

2014

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Accurate Estimation Technique of Low-Frequency Noise in NAND Flash Cell Array

IEEE electron device letters, 2016-06, Vol.37 (6), p.724-727

2016

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Development of an Advanced TDDB Analysis Model for Temperature Dependency

Electronics (Basel), 2019-09, Vol.8 (9), p.942

2019

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Reliability Analysis Framework for Time Dependent Dielectric Breakdown

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2020, 20(1), 91, pp.19-28

2020

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Electrothermal Modeling of Multi-Nanosheet FETs With Various Layouts

IEEE transactions on electron devices, 2024-04, Vol.71 (4), p.2592-2597

2024

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Analysis on the performance of a flat-plate volumetric solar collector using blended plasmonic nanofluid

Solar energy, 2016-07, Vol.132, p.247-256

2016

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Development of Organic Semiconductors Based on Quinacridone Derivatives for Organic Field-Effect Transistors: High-Voltage Logic Circuit Applications

IEEE journal of the Electron Devices Society, 2017-05, Vol.5 (3), p.209-213

2017

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Deembedding Accuracy for Device Scale and Interconnection Line Parasitics

IEEE microwave and wireless components letters, 2009-11, Vol.19 (11), p.713-715

2009

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Circuit Level Layout Optimization of MOS Transistor for RF and Noise Performance Improvements

Device and Circuit Exploration of Multi-Nanosheet Transistor for Sub-3 nm Technology Node

Non-volatile logic-in-memory ternary content addressable memory circuit with floating gate field effect transistor

Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory Devices

Investigation of Electrothermal Behaviors of 5-nm Bulk FinFET

Logic-in-memory application of ferroelectric-based WS2-channel field-effect transistors for improved area and energy efficiency

Device and Circuit Analysis of Double Gate Field Effect Transistor with Mono-Layer WS2-Channel at Sub-2 nm Technology Node

Self-heating and Corner Rounding Effects on Time Dependent Dielectric Breakdown of Stacked Multi-Nanosheet FETs

Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET)

Investigation on the effects of interconnect RC in 3nm technology node using Path-Finding Process Design Kit

Modulation of Contact Resistance of Dual‐Gated MoS2 FETs Using Fermi‐Level Pinning‐Free Antimony Semi‐Metal Contacts

Study on the Circuit Performance of Various Interconnect Metal Materials in the Latest Process Nodes

Temporal Noise Analysis and Reduction Method in CMOS Image Sensor Readout Circuit

Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage

Large-Scale Training in Neural Compact Models for Accurate and Adaptable MOSFET Simulation

Hyper-FET's Phase-Transition-Materials Design Guidelines for Ultra-Low Power Applications at 3 nm Technology Node

Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test Circuits

Highly Strained Si pFinFET on SiC With Good Control of Sub-Fin Leakage and Self-Heating

Accurate Estimation Technique of Low-Frequency Noise in NAND Flash Cell Array

Development of an Advanced TDDB Analysis Model for Temperature Dependency

Reliability Analysis Framework for Time Dependent Dielectric Breakdown

Electrothermal Modeling of Multi-Nanosheet FETs With Various Layouts

Analysis on the performance of a flat-plate volumetric solar collector using blended plasmonic nanofluid

Development of Organic Semiconductors Based on Quinacridone Derivatives for Organic Field-Effect Transistors: High-Voltage Logic Circuit Applications

Deembedding Accuracy for Device Scale and Interconnection Line Parasitics

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