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Analysis and compact modeling of a vertical grounded-base n-p-n bipolar transistor used as ESD protection in a smart power technology

IEEE journal of solid-state circuits, 2001-09, Vol.36 (9), p.1373-1381

2001

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Understanding the Failure Mechanisms of Protection Diodes During System Level ESD: Toward Repetitive Stresses Robustness

IEEE transactions on electron devices, 2012-01, Vol.59 (1), p.108-113

2012

Volltextzugriff (PDF)

Accurate prediction of the ESD robustness of semiconductor devices through physical simulation

2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual, 2005, p.106-111

2005

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ESD stress in RF-MEMS capacitive switches: The influence of dielectric material deposition method

2009 IEEE International Reliability Physics Symposium, 2009, p.568-572

2009

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High robustness PNP-based structure for the ESD protection of high voltage I/Os in an advanced smart power technology

2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2007, p.226-229

2007

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Pushing away the silicon limits of ESD protection structures: Exploration of crystallographic orientation

2008 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2008, p.200-203

2008

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Analysis and compact modeling of a vertical grounded-base NPN bipolar transistor used as an ESD protection in a smart power technology

Proceedings of the 2000 BIPOLAR/BiCMOS Circuits and Technology Meeting (Cat. No.00CH37124), 2000, p.28-31

2000

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Deep Trench NPN Transistor for Low-RON ESD Protection of High-Voltage I/Os in Advanced Smart Power Technology

2006 Bipolar/BiCMOS Circuits and Technology Meeting, 2006, p.1-4

2006

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Novel 3D back-to-back diodes ESD protection

Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2014, 2014, p.1-8

2014

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A Novel Method for Guard Ring Efficiency Assessment and its Applications for ESD Protection Design and Optimization

2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual, 2007, p.606-607

2007

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Behavioral ESD protection modeling to perform system level ESD efficient design

2012 Asia-Pacific Symposium on Electromagnetic Compatibility, 2012, p.401-404

2012

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TCAD and SPICE modeling help solve ESD protection issues in analog CMOS technology

2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595), 2002, Vol.2, p.749-752 vol.2

2002

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Investigation of statistical tools to analyze repetitive HMM stress endurance of system-level ESD protection

EOS/ESD Symposium Proceedings, 2011, p.1-9

2011

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Characterization and modeling methodology for IC's ESD susceptibility at system level using VF-TLP tester

2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2007, p.5B.1-1-5B.1-7

2007

Volltextzugriff (PDF)

ESD system level characterization and modeling methods applied to a LIN transceiver

EOS/ESD Symposium Proceedings, 2011, p.1-9

2011

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Failure Mechanisms of AIN based RF-MEMS Switches Under DC and ESD Stresses

2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2007, p.120-123

2007

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ESD induced latent defects in CMOS ICs and reliability impact

2004 Electrical Overstress/Electrostatic Discharge Symposium, 2004, p.1-8

2004

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Optimizing pulsed OBIC technique for ESD defect localization

2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2006, p.270-275

2006

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Investigation on Statistical Tools to Analyze Repetitive-Electrostatic-Discharge Endurance of System-Level Protections

IEEE transactions on device and materials reliability, 2012-12, Vol.12 (4), p.607-614

2012

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Investigation of Modeling System ESD Failure and Probability Using IBIS ESD Models

IEEE transactions on device and materials reliability, 2012-12, Vol.12 (4), p.599-606

2012

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Analysis and compact modeling of a vertical grounded-base n-p-n bipolar transistor used as ESD protection in a smart power technology

Understanding the Failure Mechanisms of Protection Diodes During System Level ESD: Toward Repetitive Stresses Robustness

Accurate prediction of the ESD robustness of semiconductor devices through physical simulation

ESD stress in RF-MEMS capacitive switches: The influence of dielectric material deposition method

High robustness PNP-based structure for the ESD protection of high voltage I/Os in an advanced smart power technology

Pushing away the silicon limits of ESD protection structures: Exploration of crystallographic orientation

Analysis and compact modeling of a vertical grounded-base NPN bipolar transistor used as an ESD protection in a smart power technology

Deep Trench NPN Transistor for Low-RON ESD Protection of High-Voltage I/Os in Advanced Smart Power Technology

Novel 3D back-to-back diodes ESD protection

A Novel Method for Guard Ring Efficiency Assessment and its Applications for ESD Protection Design and Optimization

Behavioral ESD protection modeling to perform system level ESD efficient design

TCAD and SPICE modeling help solve ESD protection issues in analog CMOS technology

Investigation of statistical tools to analyze repetitive HMM stress endurance of system-level ESD protection

Characterization and modeling methodology for IC's ESD susceptibility at system level using VF-TLP tester

ESD system level characterization and modeling methods applied to a LIN transceiver

Failure Mechanisms of AIN based RF-MEMS Switches Under DC and ESD Stresses

ESD induced latent defects in CMOS ICs and reliability impact

Optimizing pulsed OBIC technique for ESD defect localization

Investigation on Statistical Tools to Analyze Repetitive-Electrostatic-Discharge Endurance of System-Level Protections

Investigation of Modeling System ESD Failure and Probability Using IBIS ESD Models

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