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Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

IEEE transactions on electron devices, 2013-02, Vol.60 (2), p.727-732

2013

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Formation and Characterization of Filamentary Current Paths in HfO2-Based Resistive Switching Structures

IEEE electron device letters, 2012-07, Vol.33 (7), p.1057-1059

2012

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Performance and Modeling of Si-Nanocrystal Double-Layer Memory Devices With High- k Control Dielectrics

IEEE transactions on electron devices, 2012-04, Vol.59 (4), p.933-940

2012

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Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs

Solid-state electronics, 2013-06, Vol.84, p.46-52

2013

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Modeling the Independent Double Gate Transistor in Accumulation Regime for 1TDRAM Application

IEEE transactions on electron devices, 2010-04, Vol.57 (4), p.855-865

2010

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Modeling of the programming window distribution in multinanocrystals memories

IEEE transactions on nanotechnology, 2003-12, Vol.2 (4), p.277-284

2003

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Performance of Localized-SOI MOS Devices on (110) Substrates: Impact of Channel Direction

IEEE electron device letters, 2011-08, Vol.32 (8), p.996-998

2011

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Impact of a HTO/Al2O3 bi-layer blocking oxide in nitride-trap non-volatile memories

Solid-state electronics, 2009-07, Vol.53 (7), p.786-791

2009

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Evaluation of HfAlO high- k materials for control dielectric applications in non-volatile memories

Microelectronic engineering, 2008-12, Vol.85 (12), p.2393-2399

2008

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Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10 nm width: Selected extended papers from ULIS 2012 conference

Solid-state electronics, 2013, Vol.88, p.32-36

2013

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Investigation of charge-trap memories with AlN based band engineered storage layers: Special Issue Devoted to the 2nd International Memory Workshop (IMW 2010)

Solid-state electronics, 2011, Vol.58 (1), p.68-74

2011

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3D nanowire gate-all-around transistors : Specific integration and electrical features : Ultimate integration on silicon conference 2007

Solid-state electronics, 2008, Vol.52 (4), p.519-525

2008

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Breakdown mechanisms in ultra-thin oxides: impact of carrier energy and current through substrate hot carrier stress study

Microelectronic engineering, 2004-04, Vol.72 (1), p.10-15

2004

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Tuning the dipole at the High-k/SiO2 interface in advanced metal gate stacks

Microelectronic engineering, 2009, Vol.86 (7-9), p.1740-1742

2009

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Trapping and detrapping mechanism in hafnium based dielectrics characterized by pulse gate voltage techniques [CMOS transistors]

IEEE International Integrated Reliability Workshop Final Report, 2004, 2004, p.125-127

2004

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Nano Crystal Memory Devices Characterization Using the Charge Pumping Technique

32nd European Solid-State Device Research Conference, 2002, p.235-238

2002

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Low temperature electrical characterization of metal-nitrided oxide-silicon field effect transistors

Journal of applied physics, 1993-05, Vol.73 (10), p.5241-5253

1993

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A simple characterization method for silicon-on-insulator materials using a depletion-mode MOSFET

IEEE electron device letters, 1990-11, Vol.11 (11), p.552-555

1990

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Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

Formation and Characterization of Filamentary Current Paths in HfO2-Based Resistive Switching Structures

Performance and Modeling of Si-Nanocrystal Double-Layer Memory Devices With High- k Control Dielectrics

Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs

Modeling the Independent Double Gate Transistor in Accumulation Regime for 1TDRAM Application

Modeling of the programming window distribution in multinanocrystals memories

Performance of Localized-SOI MOS Devices on (110) Substrates: Impact of Channel Direction

Impact of a HTO/Al2O3 bi-layer blocking oxide in nitride-trap non-volatile memories

Evaluation of HfAlO high- k materials for control dielectric applications in non-volatile memories

Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10 nm width: Selected extended papers from ULIS 2012 conference

Investigation of charge-trap memories with AlN based band engineered storage layers: Special Issue Devoted to the 2nd International Memory Workshop (IMW 2010)

3D nanowire gate-all-around transistors : Specific integration and electrical features : Ultimate integration on silicon conference 2007

Breakdown mechanisms in ultra-thin oxides: impact of carrier energy and current through substrate hot carrier stress study

Tuning the dipole at the High-k/SiO2 interface in advanced metal gate stacks

Trapping and detrapping mechanism in hafnium based dielectrics characterized by pulse gate voltage techniques [CMOS transistors]

Nano Crystal Memory Devices Characterization Using the Charge Pumping Technique

Low temperature electrical characterization of metal-nitrided oxide-silicon field effect transistors

A simple characterization method for silicon-on-insulator materials using a depletion-mode MOSFET

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