UB Paderborn / Katalog / Suche / in CDI

Sortiert nach

Einfacher Volltextzugriff von (fast) überall

Installieren Sie die LibKey Nomad-Browsererweiterung und erhalten Sie von vielen Webseiten einfachen Zugriff auf lizenzierte Volltexte oder Open Access Publikationen. Mehr erfahren...

A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs

IEEE transactions on computers, 2016-11, Vol.65 (11), p.3265-3279

2016

Volltextzugriff (PDF)

LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-Theory Based Analytical Verification

IEEE transactions on computers, 2018-08, Vol.67 (8), p.1153-1166

2018

Volltextzugriff (PDF)

EbDa: A new theory on design and verification of deadlock-free interconnection networks

2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), 2017, p.703-715

2017

Volltextzugriff (PDF)

First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip

IEEE transactions on computers, 2018-10, Vol.67 (10), p.1430-1444

2018

Volltextzugriff (PDF)

Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing

IEEE transactions on computers, 2014-03, Vol.63 (3), p.718-733

2014

Volltextzugriff (PDF)

Efficient Design-for-Test Approach for Networks-on-Chip

IEEE transactions on computers, 2019-02, Vol.68 (2), p.198-213

2019

Volltextzugriff (PDF)

ECDR ^2: Error Corrector and Detector Relocation Router for Network-on-Chip

IEEE transactions on computers, 2021-04, Vol.70 (4), p.606-613

2021

Volltextzugriff (PDF)

Fault-tolerant routing algorithm for 3D NoC using hamiltonian path strategy

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, p.1601-1604

2013

Volltextzugriff (PDF)

Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip

Journal of systems architecture, 2013-08, Vol.59 (7), p.516-527

2013

Volltextzugriff (PDF)

Non-Blocking Testing for Network-on-Chip

IEEE transactions on computers, 2016-03, Vol.65 (3), p.679-692

2016

Volltextzugriff (PDF)

HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks

2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip, 2012, p.19-26

2012

Volltextzugriff (PDF)

In-order delivery approach for 2D and 3D NoCs

The Journal of supercomputing, 2015-08, Vol.71 (8), p.2877-2899, Article 2877

2015

Volltextzugriff (PDF)

Tolerating transient illegal turn faults in NoCs

Microprocessors and microsystems, 2016-06, Vol.43 (SI), p.104-115

2016

Volltextzugriff (PDF)

CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks

2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, p.320-325

2012

Volltextzugriff (PDF)

A generic adaptive path-based routing method for MPSoCs

Journal of systems architecture, 2011, Vol.57 (1), p.109-120

2011

Volltextzugriff (PDF)

CoBRA: Low cost compensation of TSV failures in 3D-NoC

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2016, p.115-120

2016

Volltextzugriff (PDF)

Minimizing the system impact of router faults by means of reconfiguration and adaptive routing

Microprocessors and microsystems, 2017-06, Vol.51, p.252-263

2017

Volltextzugriff (PDF)

CARS: Congestion-aware request scheduler for network interfaces in NoC-based manycore systems

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, p.1048-1051

2013

Volltextzugriff (PDF)

Fault tolerant and highly adaptive routing for 2D NoCs

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014, p.104-109

2014

Volltextzugriff (PDF)

Rescuing healthy cores against disabled routers

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014, p.98-103

2014

Volltextzugriff (PDF)

NoD: Network-on-Die as a standalone NoC for heterogeneous many-core systems in 2.5D ICs

2017 19TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS), 2017, p.1-6

2017

Volltextzugriff (PDF)

MD: Minimal path-based fault-tolerant routing in on-Chip Networks

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013, p.35-40

2013

Volltextzugriff (PDF)

Minimal-path fault-tolerant approach using connection-retaining structure in Networks-on-Chip

2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013, p.1-8

2013

Volltextzugriff (PDF)

An Adaptive, Low Restrictive and Fault Resilient Routing Algorithm for 3D Network-on-Chip

2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, 2015, p.392-395

2015

Volltextzugriff (PDF)

Optimizing dynamic mapping techniques for on-line NoC test

2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2018, p.227-232

2018

Volltextzugriff (PDF)

1 – 25 von 51

Menü

Weitere Dienste

Einstellungen

A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs

LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-Theory Based Analytical Verification

EbDa: A new theory on design and verification of deadlock-free interconnection networks

First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip

Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing

Efficient Design-for-Test Approach for Networks-on-Chip

ECDR ^2: Error Corrector and Detector Relocation Router for Network-on-Chip

Fault-tolerant routing algorithm for 3D NoC using hamiltonian path strategy

Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip

Non-Blocking Testing for Network-on-Chip

HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks

In-order delivery approach for 2D and 3D NoCs

Tolerating transient illegal turn faults in NoCs

CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks

A generic adaptive path-based routing method for MPSoCs

CoBRA: Low cost compensation of TSV failures in 3D-NoC

Minimizing the system impact of router faults by means of reconfiguration and adaptive routing

CARS: Congestion-aware request scheduler for network interfaces in NoC-based manycore systems

Fault tolerant and highly adaptive routing for 2D NoCs

Rescuing healthy cores against disabled routers

NoD: Network-on-Die as a standalone NoC for heterogeneous many-core systems in 2.5D ICs

MD: Minimal path-based fault-tolerant routing in on-Chip Networks

Minimal-path fault-tolerant approach using connection-retaining structure in Networks-on-Chip

An Adaptive, Low Restrictive and Fault Resilient Routing Algorithm for 3D Network-on-Chip

Optimizing dynamic mapping techniques for on-line NoC test

Aktive Filter

Suchergebnisse filtern