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On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells

IEEE transactions on electron devices, 2011-08, Vol.58 (8), p.2326-2336

2011

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IEEE_Xplore

Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

IEEE transactions on electron devices, 2013-02, Vol.60 (2), p.727-732

2013

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IEEE_Xplore

Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2013-03, Vol.31 (2)

2013

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Enhanced thermal performances of silicon-on-diamond wafers incorporating ultrathin nanocrystalline diamond and silicon layers: Raman and micro-Raman analysis

Journal of applied physics, 2011-10, Vol.110 (8), p.084901-084901-9

2011

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Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

Solid-state electronics, 2024-04, Vol.214, p.108865, Article 108865

2024

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Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

Solid-state electronics, 2023-10, Vol.208, p.108716, Article 108716

2023

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Multi- V T UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

IEEE transactions on electron devices, 2011-08, Vol.58 (8), p.2473-2482

2011

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Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K

Solid-state electronics, 2022-08, Vol.194, p.108337, Article 108337

2022

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Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors

Solid-state electronics, 2023-10, Vol.208, p.108737, Article 108737

2023

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Electrical characterization of stacked SOI nanowires at low temperatures

Solid-state electronics, 2022-05, Vol.191, p.108260, Article 108260

2022

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BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

IEEE transactions on electron devices, 2012-08, Vol.59 (8), p.2019-2026

2012

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IEEE_Xplore

Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs

Solid-state electronics, 2019-09, Vol.159, p.83-89

2019

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Analog characteristics of n-type vertically stacked nanowires

Solid-state electronics, 2021-11, Vol.185, p.108127, Article 108127

2021

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Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Microelectronic engineering, 2017-06, Vol.178, p.17-20

2017

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A New Method for Series Resistance Extraction of Nanometer MOSFETs

IEEE transactions on electron devices, 2017-07, Vol.64 (7), p.2797-2803

2017

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IEEE_Xplore

Low-Frequency Noise Sources in Advanced UTBB FD-SOI MOSFETs

IEEE transactions on electron devices, 2014-04, Vol.61 (4), p.1161-1167

2014

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IEEE_Xplore

A Model of Fringing Fields in Short-Channel Planar and Triple-Gate SOI MOSFETs

IEEE transactions on electron devices, 2007-06, Vol.54 (6), p.1366-1375

2007

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IEEE_Xplore

Electrical characterization of vertically stacked p-FET SOI nanowires

Solid-state electronics, 2018-03, Vol.141, p.84-91

2018

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3D analytical modelling of subthreshold characteristics in vertical Multiple-gate FinFET transistors

Solid-state electronics, 2011-11, Vol.65-66, p.94-102

2011

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Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control

IEEE transactions on electron devices, 2014-04, Vol.61 (4), p.969-975

2014

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IEEE_Xplore

Strain effect on mobility in nanowire MOSFETs down to 10 nm width: Geometrical effects and piezoresistive model

Solid-state electronics, 2016-11, Vol.125, p.175-181

2016

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High-Performance Ultrathin Body c-SiGe Channel FDSOI pMOSFETs Featuring SiGe Source and Drain: Vth Tuning, Variability, Access Resistance, and Mobility Issues

IEEE transactions on electron devices, 2013-05, Vol.60 (5), p.1568-1574

2013

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High tolerance to total ionizing dose of Ω -shaped gate field-effect transistors

Applied physics letters, 2006-05, Vol.88 (22), p.223511-223511-3

2006

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Benefits and challenges of FDSOI technology for 14nm node

IEEE 2011 International SOI Conference, 2011, p.1-21

Faynot, O.

2011

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IEEE_Xplore

SOI 1T-DRAM cells with variable channel length and thickness: Experimental comparison of programming mechanisms

Solid-state electronics, 2011-11, Vol.65-66, p.256-262

2011

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On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells

Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Enhanced thermal performances of silicon-on-diamond wafers incorporating ultrathin nanocrystalline diamond and silicon layers: Raman and micro-Raman analysis

Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

Multi- V T UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K

Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors

Electrical characterization of stacked SOI nanowires at low temperatures

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs

Analog characteristics of n-type vertically stacked nanowires

Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

A New Method for Series Resistance Extraction of Nanometer MOSFETs

Low-Frequency Noise Sources in Advanced UTBB FD-SOI MOSFETs

A Model of Fringing Fields in Short-Channel Planar and Triple-Gate SOI MOSFETs

Electrical characterization of vertically stacked p-FET SOI nanowires

3D analytical modelling of subthreshold characteristics in vertical Multiple-gate FinFET transistors

Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control

Strain effect on mobility in nanowire MOSFETs down to 10 nm width: Geometrical effects and piezoresistive model

High-Performance Ultrathin Body c-SiGe Channel FDSOI pMOSFETs Featuring SiGe Source and Drain: Vth Tuning, Variability, Access Resistance, and Mobility Issues

High tolerance to total ionizing dose of Ω -shaped gate field-effect transistors

Benefits and challenges of FDSOI technology for 14nm node

SOI 1T-DRAM cells with variable channel length and thickness: Experimental comparison of programming mechanisms

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