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Gate-based high fidelity spin readout in a CMOS device

Nature nanotechnology, 2019-08, Vol.14 (8), p.737-741

2019

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Gate-Sensing Coherent Charge Oscillations in a Silicon Field-Effect Transistor

Nano letters, 2016-03, Vol.16 (3), p.1614-1619

2016

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Few-Electron Edge-State Quantum Dots in a Silicon Nanowire Field-Effect Transistor

Nano letters, 2014-04, Vol.14 (4), p.2094-2098

2014

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pH Quantification in Human Dermal Interstitial Fluid Using Ultra-Thin SOI Silicon Nanowire ISFETs and a High-Sensitivity Constant-Current Approach

Biosensors (Basel), 2023-09, Vol.13 (10), p.908

2023

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Integration of Ultra-Low Volume Pneumatic Microfluidics with a Three-Dimensional Electrode Network for On-Chip Biochemical Sensing

Micromachines (Basel), 2021-06, Vol.12 (7), p.762

2021

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Aptasensors based on silicon nanowire field-effect transistors for electrical detection of thrombin

Microelectronic engineering, 2024-03, Vol.286, p.112130, Article 112130

2024

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Reduction of random telegraph noise by high-pressure deuterium annealing for p-type omega-gate nanowire FET

Nanotechnology, 2020-10, Vol.31 (41), p.415201-415201

2020

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Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors

Microelectronic engineering, 2019-07, Vol.215, p.111005, Article 111005

2019

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On the Application of Junctionless Nanowire Transistors in Basic Analog Building Blocks

IEEE transactions on nanotechnology, 2021, Vol.20, p.234-242

2021

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Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Microelectronic engineering, 2017-06, Vol.178, p.17-20

2017

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Level Spectrum and Charge Relaxation in a Silicon Double Quantum Dot Probed by Dual-Gate Reflectometry

Nano letters, 2017-02, Vol.17 (2), p.1001-1006

2017

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Quantum Dot Made in Metal Oxide Silicon-Nanowire Field Effect Transistor Working at Room Temperature

Nano letters, 2015-05, Vol.15 (5), p.2958-2964

2015

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A determinist method solving the Wigner transport equation for quantum transport in silicon nanowires

Journal of physics. Conference series, 2009-11, Vol.193 (1), p.012038

2009

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Impact of channel width on back biasing effect in tri-gate MOSFET

Microelectronic engineering, 2014-02, Vol.114, p.91-97

2014

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Atmospheric Pressure Selective Epitaxial Growth of Heavily in-situ Phosphorous-Doped Si(:C) Raised Sources and Drains

ECS transactions, 2016, Vol.75 (8), p.361-371

2016

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Electrical Characterization and Parameter Extraction of Junctionless Nanowire Transistors

Journal of nano research, 2016-02, Vol.39, p.17-33

2016

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Demonstration of Single Hole Transistor and Hybrid Circuits for Multivalued Logic and Memory Applications up to 350 K Using CMOS Silicon Nanowires

Advanced electronic materials, 2016-04, Vol.2 (4), p.n/a

2016

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(Invited) Germanium Enrichment for Planar-, Fin- and Nanowire-Channel MOSFETs Made on SOI

ECS transactions, 2016, Vol.75 (8), p.505-512

2016

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Ω-Gate Nanowire P-FET with cSiGe Channel Epitaxied on Strained-SOI Substrates

ECS transactions, 2016, Vol.75 (8), p.59-65

2016

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Comparison of low-temperature electrical characteristics of gate-all-around nanowire FETs, Fin FETs and fully-depleted SOI FETs

Microelectronics and reliability, 2011-05, Vol.51 (5), p.885-888

2011

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Evidences on the Physical Origin of the Unexpected Transport Degradation in Ultimate n-FDSOI Devices

IEEE transactions on nanotechnology, 2009-03, Vol.8 (2), p.167-173

2009

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Experimental Comparison of Junctionless and Inversion-Mode Nanowire MOSFETs Electrical Properties at High Temperatures

2022 36th Symposium on Microelectronics Technology (SBMICRO), 2022, p.1-4

2022

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Simulation, modelling and characterisation of quasi-ballistic transport in nanometer sized field effect transistors: from TCAD to atomistic simulation

International journal of nanotechnology., 2010, Vol.7 (4/5/6/7/8), p.348

2010

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Analysis of Variability in Transconductance and Mobility of Nanowire Transistors

2022 36th Symposium on Microelectronics Technology (SBMICRO), 2022, p.1-4

2022

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Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs

2021 35th Symposium on Microelectronics Technology and Devices (SBMicro), 2021, p.1-4

2021

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Gate-based high fidelity spin readout in a CMOS device

Gate-Sensing Coherent Charge Oscillations in a Silicon Field-Effect Transistor

Few-Electron Edge-State Quantum Dots in a Silicon Nanowire Field-Effect Transistor

pH Quantification in Human Dermal Interstitial Fluid Using Ultra-Thin SOI Silicon Nanowire ISFETs and a High-Sensitivity Constant-Current Approach

Integration of Ultra-Low Volume Pneumatic Microfluidics with a Three-Dimensional Electrode Network for On-Chip Biochemical Sensing

Aptasensors based on silicon nanowire field-effect transistors for electrical detection of thrombin

Reduction of random telegraph noise by high-pressure deuterium annealing for p-type omega-gate nanowire FET

Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors

On the Application of Junctionless Nanowire Transistors in Basic Analog Building Blocks

Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Level Spectrum and Charge Relaxation in a Silicon Double Quantum Dot Probed by Dual-Gate Reflectometry

Quantum Dot Made in Metal Oxide Silicon-Nanowire Field Effect Transistor Working at Room Temperature

A determinist method solving the Wigner transport equation for quantum transport in silicon nanowires

Impact of channel width on back biasing effect in tri-gate MOSFET

Atmospheric Pressure Selective Epitaxial Growth of Heavily in-situ Phosphorous-Doped Si(:C) Raised Sources and Drains

Electrical Characterization and Parameter Extraction of Junctionless Nanowire Transistors

Demonstration of Single Hole Transistor and Hybrid Circuits for Multivalued Logic and Memory Applications up to 350 K Using CMOS Silicon Nanowires

(Invited) Germanium Enrichment for Planar-, Fin- and Nanowire-Channel MOSFETs Made on SOI

Ω-Gate Nanowire P-FET with cSiGe Channel Epitaxied on Strained-SOI Substrates

Comparison of low-temperature electrical characteristics of gate-all-around nanowire FETs, Fin FETs and fully-depleted SOI FETs

Evidences on the Physical Origin of the Unexpected Transport Degradation in Ultimate n-FDSOI Devices

Experimental Comparison of Junctionless and Inversion-Mode Nanowire MOSFETs Electrical Properties at High Temperatures

Simulation, modelling and characterisation of quasi-ballistic transport in nanometer sized field effect transistors: from TCAD to atomistic simulation

Analysis of Variability in Transconductance and Mobility of Nanowire Transistors

Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs

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