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Monopolar Biphasic Stimulator With Discharge Function and Negative Level Shifter for Neuromodulation SoC Integration in Low-Voltage CMOS Process

IEEE transactions on biomedical circuits and systems, 2021-06, Vol.15 (3), p.568-579

2021

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Using Schottky Barrier Diode to Improve Latch-Up Immunity for CMOS ICs Operating With Negative Voltage Sources

IEEE electron device letters, 2021-03, Vol.42 (3), p.395-397

2021

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A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process

IEEE transactions on biomedical circuits and systems, 2016-12, Vol.10 (6), p.1087-1099

2016

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Design of High-Voltage-Tolerant Power-Rail ESD Protection Circuit for Power Pin of Negative Voltage in Low-Voltage CMOS Processes

IEEE transactions on electron devices, 2020-01, Vol.67 (1), p.40-46

2020

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Optimization Design on Active Guard Ring to Improve Latch-Up Immunity of CMOS Integrated Circuits

IEEE transactions on electron devices, 2019-04, Vol.66 (4), p.1648-1655

2019

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Investigation of CDM ESD Protection Capability Among Power-Rail ESD Clamp Circuits in CMOS ICs With Decoupling Capacitors

IEEE journal of the Electron Devices Society, 2023, Vol.11, p.84-94

2023

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Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test

IEEE journal of solid-state circuits, 2008-11, Vol.43 (11), p.2533-2545

2008

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Study on CDM ESD Robustness Among On-Chip Decoupling Capacitors in CMOS Integrated Circuits

IEEE journal of the Electron Devices Society, 2021, Vol.9, p.881-890

2021

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Overview and Design of Mixed-Voltage I/O Buffers With Low-Voltage Thin-Oxide CMOS Transistors

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2006-09, Vol.53 (9), p.1934-1945

2006

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Design of Multi-Channel Monopolar Biphasic Stimulator for Implantable Biomedical Applications

2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), 2018, p.1-4

2018

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Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology

IEEE transactions on electron devices, 2009-08, Vol.56 (8), p.1774-1779

2009

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New Ballasting Layout Schemes to Improve ESD Robustness of I/O Buffers in Fully Silicided CMOS Process

IEEE transactions on electron devices, 2009-12, Vol.56 (12), p.3149-3159

2009

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Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2006-02, Vol.53 (2), p.235-246

2006

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Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process

IEEE transactions on circuits and systems. I, Regular papers, 2010-05, Vol.57 (5), p.1039-1047

2010

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Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of Multi-Finger ESD Protection Devices

IEEE journal of solid-state circuits, 2006-11, Vol.41 (11), p.2601-2609

2006

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Design of Mixed-Voltage I/O Buffer by Using NMOS-Blocking Technique

IEEE journal of solid-state circuits, 2006-10, Vol.41 (10), p.2324-2333

2006

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Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs

IEEE transactions on circuits and systems. II, Express briefs, 2009-05, Vol.56 (5), p.359-363

2009

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Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs

IEEE journal of solid-state circuits, 2011-02, Vol.46 (2), p.537-545

2011

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Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2006-10, Vol.53 (10), p.2187-2193

2006

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Investigation on Latch-Up Path Between I/O PMOS and Core PMOS in a 0.18-μm CMOS Process

2019 IEEE International Reliability Physics Symposium (IRPS), 2019, p.1-4

2019

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ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology

IEEE journal of solid-state circuits, 2005-11, Vol.40 (11), p.2329-2338

2005

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Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process

IEEE transactions on semiconductor manufacturing, 2003-08, Vol.16 (3), p.486-500

2003

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Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers

IEEE journal of solid-state circuits, 2002-08, Vol.37 (8), p.1046-1055

2002

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Substrate-triggered ESD protection circuit without extra process modification

IEEE journal of solid-state circuits, 2003-02, Vol.38 (2), p.295-302

2003

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A bending N-Well ballast layout to improve ESD robustness in fully-silicided CMOS technology

2010 IEEE International Reliability Physics Symposium, 2010, p.857-860

2010

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Monopolar Biphasic Stimulator With Discharge Function and Negative Level Shifter for Neuromodulation SoC Integration in Low-Voltage CMOS Process

Using Schottky Barrier Diode to Improve Latch-Up Immunity for CMOS ICs Operating With Negative Voltage Sources

A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process

Design of High-Voltage-Tolerant Power-Rail ESD Protection Circuit for Power Pin of Negative Voltage in Low-Voltage CMOS Processes

Optimization Design on Active Guard Ring to Improve Latch-Up Immunity of CMOS Integrated Circuits

Investigation of CDM ESD Protection Capability Among Power-Rail ESD Clamp Circuits in CMOS ICs With Decoupling Capacitors

Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test

Study on CDM ESD Robustness Among On-Chip Decoupling Capacitors in CMOS Integrated Circuits

Overview and Design of Mixed-Voltage I/O Buffers With Low-Voltage Thin-Oxide CMOS Transistors

Design of Multi-Channel Monopolar Biphasic Stimulator for Implantable Biomedical Applications

Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology

New Ballasting Layout Schemes to Improve ESD Robustness of I/O Buffers in Fully Silicided CMOS Process

Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations

Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process

Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of Multi-Finger ESD Protection Devices

Design of Mixed-Voltage I/O Buffer by Using NMOS-Blocking Technique

Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs

Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs

Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process

Investigation on Latch-Up Path Between I/O PMOS and Core PMOS in a 0.18-μm CMOS Process

ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology

Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process

Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers

Substrate-triggered ESD protection circuit without extra process modification

A bending N-Well ballast layout to improve ESD robustness in fully-silicided CMOS technology

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