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Enabling transparent hardware acceleration on Zynq SoC for scientific computing

SIGBED review, 2020-07, Vol.17 (1), p.30-35

2020

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A Hardware Accelerator for The Inference of a Convolutional Neural Network

Ciencia e ingeniería neogranadina, 2020-01, Vol.30 (1), p.107-116

2020

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HW/SW Co-Design of the HOG algorithm on a Xilinx Zynq SoC

Journal of parallel and distributed computing, 2017-11, Vol.109, p.50-62

2017

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A Hardware Accelerator for the Inference of a Convolutional Neural network

Ciencia e ingeniería neogranadina, 2019-11, Vol.30 (1)

2019

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An Efficient FPGA-Based Accelerator for Perceptual Weighting Filter in Speech Coding

Technical review - IETE, 2024-07, Vol.41 (4), p.441-453

2024

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Optimizing a Field-Programmable Gate Array Object Detection System Considering Processing System and Programmable Logic Load Balance

Journal of Robotics, Networking and Artificial Life, 2023, Vol.10(2), pp.105-114

2023

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Energy-efficient acceleration of MapReduce applications using FPGAs

Journal of parallel and distributed computing, 2018-09, Vol.119, p.1-17

2018

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Real-Time Energy Efficient Hand Pose Estimation: A Case Study

Sensors (Basel, Switzerland), 2020-05, Vol.20 (10), p.2828

2020

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Development and integration of DAQ system for beam current monitoring of the KOMAC linac and beamlines

Journal of the Korean Physical Society, 2024, 85(3), , pp.219-225

2024

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Laser ultrasonic time-domain synthetic aperture focusing (SAFT) co-overlay software and hardware (COSH) computing system based on ZYNQ

Frontiers in materials, 2024-01, Vol.10

2024

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Research on Dynamic Reconfiguration Technology of Neural Network Accelerator Based on Zynq

Journal of physics. Conference series, 2020-10, Vol.1650 (3), p.32093

2020

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MLP Neural Network Based Gas Classification System on Zynq SoC

IEEE access, 2016, Vol.4, p.8138-8146

2016

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FPGA accelerated model predictive control for autonomous driving

Journal of intelligent and connected vehicles, 2022-05, Vol.5 (2), p.63-71

2022

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Real-time automated image segmentation technique for cerebral aneurysm on reconfigurable system-on-chip

Journal of computational science, 2018-07, Vol.27, p.35-45

2018

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Hardware performance analysis of RSA cryptosystems on FPGA for wireless sensor nodes

International journal of intelligent networks, 2021, Vol.2, p.184-194

2021

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Design, implementation, and test of an SDR for NVIS communications

International journal of circuit theory and applications, 2019-09, Vol.47 (9), p.1502-1512

2019

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Embedded platform for local image descriptor based object detection

Applied mathematics and computation, 2015-09, Vol.267, p.419-426

2015

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FPGA embedded multichannel analyzer

Applied radiation and isotopes, 2018-11, Vol.141, p.282-287

2018

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Evaluation of Cryptographic Algorithms over an all Programmable SoC (AP SoC) Device

Journal of systemics, cybernetics and informatics, 2017-04, Vol.15 (2), p.84-91

2017

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Accelerated and optimized covariance descriptor for pedestrian detection in self-driving cars

Design automation for embedded systems, 2023-09, Vol.27 (3), p.139-163

2023

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Nuclear pulse generator embedded in FPGA

Applied radiation and isotopes, 2019-05, Vol.147, p.129-135

2019

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Exploring Sparse Visual Odometry Acceleration With High-Level Synthesis

IEEE access, 2023, Vol.11, p.70741-70763

2023

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iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing: Multiresolution Morphology-based Text and Image Segmentation

International journal of parallel programming, 2021-04, Vol.49 (2), p.253-284

2021

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Real-Time FPGA Implementation of Parallel Connected Component Labelling for a 4K Video Stream

Journal of signal processing systems, 2021-05, Vol.93 (5), p.481-498

2021

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A Comparative Study of Sorting Algorithms with FPGA Acceleration by High Level Synthesis

Computación y Sistemas, 2019-01, Vol.23 (1), p.213-230

2019

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Enabling transparent hardware acceleration on Zynq SoC for scientific computing

A Hardware Accelerator for The Inference of a Convolutional Neural Network

HW/SW Co-Design of the HOG algorithm on a Xilinx Zynq SoC

A Hardware Accelerator for the Inference of a Convolutional Neural network

An Efficient FPGA-Based Accelerator for Perceptual Weighting Filter in Speech Coding

Optimizing a Field-Programmable Gate Array Object Detection System Considering Processing System and Programmable Logic Load Balance

Energy-efficient acceleration of MapReduce applications using FPGAs

Real-Time Energy Efficient Hand Pose Estimation: A Case Study

Development and integration of DAQ system for beam current monitoring of the KOMAC linac and beamlines

Laser ultrasonic time-domain synthetic aperture focusing (SAFT) co-overlay software and hardware (COSH) computing system based on ZYNQ

Research on Dynamic Reconfiguration Technology of Neural Network Accelerator Based on Zynq

MLP Neural Network Based Gas Classification System on Zynq SoC

FPGA accelerated model predictive control for autonomous driving

Real-time automated image segmentation technique for cerebral aneurysm on reconfigurable system-on-chip

Hardware performance analysis of RSA cryptosystems on FPGA for wireless sensor nodes

Design, implementation, and test of an SDR for NVIS communications

Embedded platform for local image descriptor based object detection

FPGA embedded multichannel analyzer

Evaluation of Cryptographic Algorithms over an all Programmable SoC (AP SoC) Device

Accelerated and optimized covariance descriptor for pedestrian detection in self-driving cars

Nuclear pulse generator embedded in FPGA

Exploring Sparse Visual Odometry Acceleration With High-Level Synthesis

iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing: Multiresolution Morphology-based Text and Image Segmentation

Real-Time FPGA Implementation of Parallel Connected Component Labelling for a 4K Video Stream

A Comparative Study of Sorting Algorithms with FPGA Acceleration by High Level Synthesis

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