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CMOS Clock-Gated Synchronous Up/Down Counter With High-Speed Local Clock Generation and Compact Toggle Flip-Flop
IEEE transactions on circuits and systems. I, Regular papers, 2023-12, Vol.70 (12), p.5316-5327
2023
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Low-Power High-Speed Sense-Amplifier-Based Flip-Flops With Conditional Bridging
IEEE access, 2023, Vol.11, p.121835-121844
2023
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Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application
IEEE transactions on very large scale integration (VLSI) systems, 2017-02, Vol.25 (2), p.779-782
2017
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Conditional-capture flip-flop for statistical power reduction
IEEE journal of solid-state circuits, 2001-08, Vol.36 (8), p.1263-1271
2001
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Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation
IEEE transactions on circuits and systems. II, Express briefs, 2009-08, Vol.56 (8), p.649-653
2009
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Presetting pulse-based flip-flop
2008 IEEE International Symposium on Circuits and Systems, 2008, p.588-591
2008
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Dynamic Differential Flip-Flop without Explicit Output Latching Stage for High-Speed SoC
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2021, p.1-4
2021
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Conditional-capture flip-flop technique for statistical power reduction
2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056), 2000, p.290-291
2000
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An efficient dual-supply design for low-power mobile systems
2012 International SoC Design Conference (ISOCC), 2012, p.359-362
2012
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Variable sampling window flip-flop for low-power application
2003 IEEE International Symposium on Circuits and Systems (ISCAS), 2003, Vol.5, p.V-V
2003
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Nonoverlapping Cuspid-Pulsed Flip-Flop
2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007, p.158-161
2007
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