UB Paderborn / Katalog / Suche / in CDI

Annual ACM IEEE Design Automation Conference: Proceedings of the 39th conference on Design automation : New Orleans, Louisiana, USA; 10-14 June 2002, 2002, p.731-736

2002

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AMUSE: a minimally-unsatisfiable subformula extractor

Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004, 2004, p.518-523

2004

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IEEE_Xplore

SafeResynth: A new technique for physical synthesis

Integration (Amsterdam), 2008-07, Vol.41 (4), p.544-556

2008

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Solving modern mixed-size placement instances

Integration (Amsterdam), 2009-02, Vol.42 (2), p.262-275

2009

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A Compressed Breadth-First Search for Satisfiability

Algorithm Engineering and Experiments, 2002, p.29-42

2002

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On whitespace and stability in physical synthesis

Integration (Amsterdam), 2006-07, Vol.39 (4), p.340-362

2006

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SIMULATING QUANTUM COMPUTATION BY CONTRACTING TENSOR NETWORKS

SIAM journal on computing, 2009, Vol.38 (3), p.963-981

2009

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ENDING PIRACY OF INTEGRIITED CIRCUITS

Computer (Long Beach, Calif.), 2010, Vol.43 (10), p.30-38

2010

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Generic ILP versus specialized 0-1 ILP: an update

Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design, 2002, p.450-457

2002

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Unification of partitioning, placement and floorplanning

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004, 2004, p.550-557

2004

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IEEE_Xplore

Reversible logic circuit synthesis

Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design, 2002, p.353-360

2002

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On wirelength estimations for row-based placement

IEEE transactions on computer-aided design of integrated circuits and systems, 1999-09, Vol.18 (9), p.1265-1278

1999

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IEEE_Xplore

System-Level Interconnect Prediction SLIP 2005 workshop

Integration (Amsterdam), 2007, Vol.40 (4), p.382-446

2007

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Design and implementation of the Fiduccia-Mattheyses heuristic for VLSI netlist partitioning

Lecture notes in computer science, 1999, p.177-193

1999

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Improved a priori interconnect predictions and technology extrapolation in the GTX system : System-level interconnect prediction (SLIP)

IEEE transactions on very large scale integration (VLSI) systems, 2003, Vol.11 (1), p.3-14

2003

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Faster minimization of linear wirelength for global placement

IEEE transactions on computer-aided design of integrated circuits and systems, 1998-01, Vol.17 (1), p.3-13

1998

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IEEE_Xplore

Improving the efficiency of circuit-to-BDD conversion by gate and input ordering

Proceedings, IEEE International Conference on Computer Design, 2002, p.64-69

2002

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IEEE_Xplore

SimPL: An Algorithm for Placing VLSI Circuits

Communications of the ACM, 2013-06, Vol.56 (6), p.105-113

2013

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AMUSE: a minimally-unsatisfiable subformula extractor

SafeResynth: A new technique for physical synthesis

Solving modern mixed-size placement instances

A Compressed Breadth-First Search for Satisfiability

On whitespace and stability in physical synthesis

SIMULATING QUANTUM COMPUTATION BY CONTRACTING TENSOR NETWORKS

ENDING PIRACY OF INTEGRIITED CIRCUITS

Generic ILP versus specialized 0-1 ILP: an update

Unification of partitioning, placement and floorplanning

Reversible logic circuit synthesis

On wirelength estimations for row-based placement

System-Level Interconnect Prediction SLIP 2005 workshop

Design and implementation of the Fiduccia-Mattheyses heuristic for VLSI netlist partitioning

Improved a priori interconnect predictions and technology extrapolation in the GTX system : System-level interconnect prediction (SLIP)

Faster minimization of linear wirelength for global placement

Improving the efficiency of circuit-to-BDD conversion by gate and input ordering

SimPL: An Algorithm for Placing VLSI Circuits

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