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Comparative study of sensitive volume and triggering criteria of SEB in 600 V planar and trench IGBTs

Microelectronics and reliability, 2011-09, Vol.51 (9-11), p.1990-1994

2011

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MOS-IGBT power devices for high-temperature operation in smart power SOI technology

Microelectronics and reliability, 2011-09, Vol.51 (9-11), p.1980-1984

2011

Volltextzugriff (PDF)

Reliability of ESD protection devices designed in a 3D technology

Microelectronics and reliability, 2014-09, Vol.54 (9-10), p.2272-2277

2014

Volltextzugriff (PDF)

On-chip measurement to analyze failure mechanisms of ICs under system level ESD stress

Microelectronics and reliability, 2013-09, Vol.53 (9-11), p.1278-1283

2013

Volltextzugriff (PDF)

Electrostatic discharge failure analysis of capacitive RF MEMS switches

Microelectronics and reliability, 2007-09, Vol.47 (9), p.1818-1822

2007

Volltextzugriff (PDF)

ESD failure signature in capacitive RF MEMS switches

Microelectronics and reliability, 2008-08, Vol.48 (8), p.1237-1240

2008

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Evaluation of the ESD performance of local protections based on SCR or bi-SCR with dynamic or static trigger circuit in 32 nm

Microelectronics and reliability, 2010-09, Vol.50 (9), p.1379-1382

2010

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Analytical description of the injection ratio of self-biased bipolar transistors under the very high injection conditions of ESD events

Solid-state electronics, 2008-05, Vol.52 (5), p.663-674

2008

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Failure mechanisms of discrete protection device subjected to repetitive electrostatic discharges (ESD)

Microelectronics and reliability, 2009-09, Vol.49 (9), p.1103-1106

2009

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Application of various optical techniques for ESD defect localization

Microelectronics and reliability, 2006-09, Vol.46 (9), p.1563-1568

2006

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Latch-up ring design guidelines to improve electrostatic discharge (ESD) protection scheme efficiency

IEEE journal of solid-state circuits, 2004-10, Vol.39 (10), p.1778-1782

2004

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Identification of the physical signatures of CDM induced latent defects into a DC–DC converter using low frequency noise measurements

Microelectronics and reliability, 2007-09, Vol.47 (9), p.1456-1461

2007

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Long-term reliability of silicon bipolar transistors subjected to low constraints

Microelectronics and reliability, 2007-09, Vol.47 (9), p.1590-1594

2007

Volltextzugriff (PDF)

Understanding the Failure Mechanisms of Protection Diodes During System Level ESD: Toward Repetitive Stresses Robustness

IEEE transactions on electron devices, 2012-01, Vol.59 (1), p.108-113

2012

Volltextzugriff (PDF)

Study of the ESD defects impact on ICs reliability

Microelectronics and reliability, 2004-09, Vol.44 (9), p.1811-1815

2004

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A System-Level Electrostatic-Discharge-Protection Modeling Methodology for Time-Domain Analysis

IEEE transactions on electromagnetic compatibility, 2013-02, Vol.55 (1), p.45-57

2013

Volltextzugriff (PDF)

Different Failure signatures of multiple TLP and HBM Stresses in an ESD robust protection structure

Microelectronics and reliability, 2005-09, Vol.45 (9), p.1415-1420

2005

Volltextzugriff (PDF)

Building-up of system level ESD modeling: Impact of a decoupling capacitance on ESD propagation : ADVANCES IN ELECTROSTATIC DISCHARGE (ESD) PROTECTION FOR ICs

Microelectronics and reliability, 2013, Vol.53 (2), p.221-228

2013

Volltextzugriff (PDF)

Low Frequency Noise Measurements for ESD Latent Defect Detection in High Reliability Applications

Microelectronics and reliability, 2004-09, Vol.44 (9), p.1781-1786

2004

Volltextzugriff (PDF)

CMOS current conveyor

Electronics letters, 1992, Vol.28 (24), p.2261-2262

1992

Volltextzugriff (PDF)

Substrate current control in smart power IC's with a flexible protection structure

Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, 2002, p.36-40

2002

Volltextzugriff (PDF)

Substrate current protection in smart power IC's

12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094), 2000, p.169-172

2000

Volltextzugriff (PDF)

The smart power high-side switch: description of a specific technology, its basic devices, and monitoring circuitries

IEEE transactions on electron devices, 1990-04, Vol.37 (4), p.1154-1161

1990

Volltextzugriff (PDF)

Application of a floating well concept to a latch-up-free, low-cost, smart power high-side switch technology

IEEE transactions on electron devices, 1993-07, Vol.40 (7), p.1340-1342

1993

Volltextzugriff (PDF)

Capacitive coupling of floating body well to sensitive nodes prevents high-resistance CMOS circuit from latching-up

Electronics letters, 1989-06, Vol.25 (13), p.860-861

1989

Volltextzugriff (PDF)

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Comparative study of sensitive volume and triggering criteria of SEB in 600 V planar and trench IGBTs

MOS-IGBT power devices for high-temperature operation in smart power SOI technology

Reliability of ESD protection devices designed in a 3D technology

On-chip measurement to analyze failure mechanisms of ICs under system level ESD stress

Electrostatic discharge failure analysis of capacitive RF MEMS switches

ESD failure signature in capacitive RF MEMS switches

Evaluation of the ESD performance of local protections based on SCR or bi-SCR with dynamic or static trigger circuit in 32 nm

Analytical description of the injection ratio of self-biased bipolar transistors under the very high injection conditions of ESD events

Failure mechanisms of discrete protection device subjected to repetitive electrostatic discharges (ESD)

Application of various optical techniques for ESD defect localization

Latch-up ring design guidelines to improve electrostatic discharge (ESD) protection scheme efficiency

Identification of the physical signatures of CDM induced latent defects into a DC–DC converter using low frequency noise measurements

Long-term reliability of silicon bipolar transistors subjected to low constraints

Understanding the Failure Mechanisms of Protection Diodes During System Level ESD: Toward Repetitive Stresses Robustness

Study of the ESD defects impact on ICs reliability

A System-Level Electrostatic-Discharge-Protection Modeling Methodology for Time-Domain Analysis

Different Failure signatures of multiple TLP and HBM Stresses in an ESD robust protection structure

Building-up of system level ESD modeling: Impact of a decoupling capacitance on ESD propagation : ADVANCES IN ELECTROSTATIC DISCHARGE (ESD) PROTECTION FOR ICs

Low Frequency Noise Measurements for ESD Latent Defect Detection in High Reliability Applications

CMOS current conveyor

Substrate current control in smart power IC's with a flexible protection structure

Substrate current protection in smart power IC's

The smart power high-side switch: description of a specific technology, its basic devices, and monitoring circuitries

Application of a floating well concept to a latch-up-free, low-cost, smart power high-side switch technology

Capacitive coupling of floating body well to sensitive nodes prevents high-resistance CMOS circuit from latching-up

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