UB Paderborn / Katalog / Suche / in CDI

CNP: An FPGA-based processor for Convolutional Networks

2009 International Conference on Field Programmable Logic and Applications, 2009, p.32-37

2009

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Improving the quality of a Physical Unclonable Function using configurable Ring Oscillators

2009 International Conference on Field Programmable Logic and Applications, 2009, p.703-707

2009

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Performance comparison of FPGA, GPU and CPU in image processing

2009 International Conference on Field Programmable Logic and Applications, 2009, p.126-131

2009

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Run-time Partial Reconfiguration speed investigation and architectural design space exploration

2009 International Conference on Field Programmable Logic and Applications, 2009, p.498-502

2009

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FPGA partial reconfiguration via configuration scrubbing

2009 International Conference on Field Programmable Logic and Applications, 2009, p.99-104

2009

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Exploring reconfigurable architectures for explicit finite difference option pricing models

2009 International Conference on Field Programmable Logic and Applications, 2009, p.73-78

2009

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A highly scalable Restricted Boltzmann Machine FPGA implementation

2009 International Conference on Field Programmable Logic and Applications, 2009, p.367-372

2009

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A novel SRAM-based FPGA architecture for efficient TMR fault tolerance support

2009 International Conference on Field Programmable Logic and Applications, 2009, p.193-198

2009

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Generating high-performance custom floating-point pipelines

2009 International Conference on Field Programmable Logic and Applications, 2009, p.59-64

2009

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Large multipliers with fewer DSP blocks

2009 International Conference on Field Programmable Logic and Applications, 2009, p.250-255

2009

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A new deadlock-free fault-tolerant routing algorithm for NoC interconnections

2009 International Conference on Field Programmable Logic and Applications, 2009, p.326-331

2009

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Exploiting fast carry-chains of FPGAs for designing compressor trees

2009 International Conference on Field Programmable Logic and Applications, 2009, p.242-249

2009

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Clock gating architectures for FPGA power reduction

2009 International Conference on Field Programmable Logic and Applications, 2009, p.112-118

2009

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A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs

2009 International Conference on Field Programmable Logic and Applications, 2009, p.569-573

2009

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Towards a unique FPGA-based identification circuit using process variations

2009 International Conference on Field Programmable Logic and Applications, 2009, p.397-402

2009

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Coarse-grained dynamically reconfigurable architecture with flexible reliability

2009 International Conference on Field Programmable Logic and Applications, 2009, p.186-192

2009

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Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors

2009 International Conference on Field Programmable Logic and Applications, 2009, p.65-72

2009

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CREMA: A coarse-grain reconfigurable array with mapping adaptiveness

2009 International Conference on Field Programmable Logic and Applications, 2009, p.708-712

2009

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Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation

2009 International Conference on Field Programmable Logic and Applications, 2009, p.138-145

2009

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Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems

2009 International Conference on Field Programmable Logic and Applications, 2009, p.212-217

2009

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Reconfigurable fault tolerance: A framework for environmentally adaptive fault mitigation in space

2009 International Conference on Field Programmable Logic and Applications, 2009, p.199-204

2009

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A novel states recovery technique for the TMR softcore processor

2009 International Conference on Field Programmable Logic and Applications, 2009, p.543-546

2009

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Cooperative multithreading in dynamically reconfigurable systems

2009 International Conference on Field Programmable Logic and Applications, 2009, p.551-554

2009

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Compact FPGA implementation of Camellia

2009 International Conference on Field Programmable Logic and Applications, 2009, p.658-661

2009

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MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link

2009 International Conference on Field Programmable Logic and Applications, 2009, p.6-11

2009

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CNP: An FPGA-based processor for Convolutional Networks

Improving the quality of a Physical Unclonable Function using configurable Ring Oscillators

Performance comparison of FPGA, GPU and CPU in image processing

Run-time Partial Reconfiguration speed investigation and architectural design space exploration

FPGA partial reconfiguration via configuration scrubbing

Exploring reconfigurable architectures for explicit finite difference option pricing models

A highly scalable Restricted Boltzmann Machine FPGA implementation

A novel SRAM-based FPGA architecture for efficient TMR fault tolerance support

Generating high-performance custom floating-point pipelines

Large multipliers with fewer DSP blocks

A new deadlock-free fault-tolerant routing algorithm for NoC interconnections

Exploiting fast carry-chains of FPGAs for designing compressor trees

Clock gating architectures for FPGA power reduction

A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs

Towards a unique FPGA-based identification circuit using process variations

Coarse-grained dynamically reconfigurable architecture with flexible reliability

Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors

CREMA: A coarse-grain reconfigurable array with mapping adaptiveness

Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation

Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems

Reconfigurable fault tolerance: A framework for environmentally adaptive fault mitigation in space

A novel states recovery technique for the TMR softcore processor

Cooperative multithreading in dynamically reconfigurable systems

Compact FPGA implementation of Camellia

MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link

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