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Analysis of the Electrical Parameters of SOI Junctionless Nanowire Transistors at High Temperatures

IEEE journal of the Electron Devices Society, 2021, Vol.9, p.492-499

2021

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Low-temperature electrical characterization of junctionless transistors

Solid-state electronics, 2013-02, Vol.80, p.135-141

2013

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High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

IEEE journal of the Electron Devices Society, 2023-01, Vol.11, p.1-1

2023

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Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

IEEE transactions on electron devices, 2013-02, Vol.60 (2), p.727-732

2013

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IEEE_Xplore

Low-frequency noise behavior of junctionless transistors compared to inversion-mode transistors

Solid-state electronics, 2013-03, Vol.81, p.101-104

2013

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Development of a CMOS Route for Electron Pumps to Be Used in Quantum Metrology

Technologies (Basel), 2016-03, Vol.4 (1), p.10

2016

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Aptasensors based on silicon nanowire field-effect transistors for electrical detection of thrombin

Microelectronic engineering, 2024-03, Vol.286, p.112130, Article 112130

2024

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Influence of interface traps position along channel in the low-frequency noise of junctionless nanowire transistors

Solid-state electronics, 2024-02, Vol.212, p.108835, Article 108835

2024

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Channel-Width-Dependent Mobility Degradation in Bulk Conduction Regime of Tri-Gate Junctionless Transistors

IEEE transactions on electron devices, 2022-06, Vol.69 (6), p.3037-3041

2022

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IEEE_Xplore

Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

Solid-state electronics, 2024-04, Vol.214, p.108865, Article 108865

2024

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Interface traps density extraction through transient measurements in junctionless transistors

Solid-state electronics, 2022-08, Vol.194, p.108302, Article 108302

2022

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Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

Solid-state electronics, 2023-10, Vol.208, p.108716, Article 108716

2023

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Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors

Microelectronic engineering, 2019-07, Vol.215, p.111005, Article 111005

2019

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Analytical Model for Low-Frequency Noise in Junctionless Nanowire Transistors

IEEE transactions on electron devices, 2020-06, Vol.67 (6), p.2536-2543, Article 2536

2020

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IEEE_Xplore

Influence of interface traps density and temperature variation on the NBTI effect in p-Type junctionless nanowire transistors

Solid-state electronics, 2021-12, Vol.186, p.108097, Article 108097

2021

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Influence of fin width variation on the electrical characteristics of n-type junctionless nanowire transistors at high temperatures

Solid-state electronics, 2021-11, Vol.185, p.108072, Article 108072

2021

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Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K

Solid-state electronics, 2022-08, Vol.194, p.108337, Article 108337

2022

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Channel width dependent subthreshold operation of tri-gate junctionless transistors

Solid-state electronics, 2020-09, Vol.171, p.107860, Article 107860

2020

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Impact of Channel Length on the Operation of Junctionless Transistors With Substrate Biasing

IEEE transactions on electron devices, 2021-06, Vol.68 (6), p.3070-3073

2021

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IEEE_Xplore

Controlling the Effective Channel Thickness of Junctionless Transistors by Substrate Bias

IEEE transactions on electron devices, 2020-11, Vol.67 (11), p.4736-4740

2020

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IEEE_Xplore

Variability Modeling in Triple-Gate Junctionless Nanowire Transistors

IEEE transactions on electron devices, 2022-08, Vol.69 (8), p.4730-4736

2022

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IEEE_Xplore

A Simple Interpolation Model for the Carrier Mobility in Trigate and Gate-All-Around Silicon NWFETs

IEEE transactions on electron devices, 2017-06, Vol.64 (6), p.2485-2491

2017

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IEEE_Xplore

Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors

Solid-state electronics, 2023-10, Vol.208, p.108737, Article 108737

2023

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Electrical characterization of stacked SOI nanowires at low temperatures

Solid-state electronics, 2022-05, Vol.191, p.108260, Article 108260

2022

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Impact of Hot Carrier Aging on the Performance of Triple-Gate Junctionless MOSFETs

IEEE transactions on electron devices, 2020-02, Vol.67 (2), p.424-429

2020

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IEEE_Xplore

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Analysis of the Electrical Parameters of SOI Junctionless Nanowire Transistors at High Temperatures

Low-temperature electrical characterization of junctionless transistors

High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

Low-frequency noise behavior of junctionless transistors compared to inversion-mode transistors

Development of a CMOS Route for Electron Pumps to Be Used in Quantum Metrology

Aptasensors based on silicon nanowire field-effect transistors for electrical detection of thrombin

Influence of interface traps position along channel in the low-frequency noise of junctionless nanowire transistors

Channel-Width-Dependent Mobility Degradation in Bulk Conduction Regime of Tri-Gate Junctionless Transistors

Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

Interface traps density extraction through transient measurements in junctionless transistors

Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors

Analytical Model for Low-Frequency Noise in Junctionless Nanowire Transistors

Influence of interface traps density and temperature variation on the NBTI effect in p-Type junctionless nanowire transistors

Influence of fin width variation on the electrical characteristics of n-type junctionless nanowire transistors at high temperatures

Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K

Channel width dependent subthreshold operation of tri-gate junctionless transistors

Impact of Channel Length on the Operation of Junctionless Transistors With Substrate Biasing

Controlling the Effective Channel Thickness of Junctionless Transistors by Substrate Bias

Variability Modeling in Triple-Gate Junctionless Nanowire Transistors

A Simple Interpolation Model for the Carrier Mobility in Trigate and Gate-All-Around Silicon NWFETs

Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors

Electrical characterization of stacked SOI nanowires at low temperatures

Impact of Hot Carrier Aging on the Performance of Triple-Gate Junctionless MOSFETs

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