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A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS

IEEE journal of solid-state circuits, 2015-03, Vol.50 (3), p.714-723

2015

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Efficient and Accurate Statistical Analog Yield Optimization and Variation-Aware Circuit Sizing Based on Computational Intelligence Techniques

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-06, Vol.30 (6), p.793-805

2011

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An Efficient High-Frequency Linear RF Amplifier Synthesis Method Based on Evolutionary Computation and Machine Learning Techniques

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-07, Vol.31 (7), p.981-993

2012

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GASPAD: A General and Efficient mm-Wave Integrated Circuit Synthesis Method Based on Surrogate Model Assisted Evolutionary Algorithm

IEEE transactions on computer-aided design of integrated circuits and systems, 2014-02, Vol.33 (2), p.169-182

2014

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A Low-Complexity Radar Detector Outperforming OS-CFAR for Indoor Drone Obstacle Avoidance

IEEE journal of selected topics in applied earth observations and remote sensing, 2021, Vol.14, p.9162-9175

2021

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Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy

IEEE transactions on computer-aided design of integrated circuits and systems, 2009-11, Vol.28 (11), p.1627-1640

2009

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Synthesis of Integrated Passive Components for High-Frequency RF ICs Based on Evolutionary Computation and Machine Learning Techniques

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-10, Vol.30 (10), p.1458-1468

2011

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Improving the Accuracy of Spiking Neural Networks for Radar Gesture Recognition Through Preprocessing

IEEE transaction on neural networks and learning systems, 2023-06, Vol.34 (6), p.2869-2881

2023

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A 3-tier UWB-based indoor localization system for ultra-low-power sensor networks

IEEE transactions on wireless communications, 2009-06, Vol.8 (6), p.2813-2818

2009

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On the Use of Spiking Neural Networks for Ultralow-Power Radar Gesture Recognition

IEEE microwave and wireless components letters, 2022-03, Vol.32 (3), p.222-225

2022

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Analysis and Comparison of Readout Architectures and Analog-to-Digital Converters for 3D-Stacked CMOS Image Sensors

IEEE transactions on circuits and systems. I, Regular papers, 2021-08, Vol.68 (8), p.3117-3130

2021

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Recurrent sparse support vector regression machines trained by active learning in the time-domain

Expert systems with applications, 2012-09, Vol.39 (12), p.10933-10942

2012

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Assessment of Transistor Aging Models in a 28nm CMOS Technology at a Wide Range of Stress Conditions

2022 IEEE International Integrated Reliability Workshop (IIRW), 2022, p.1-6

2022

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A Reconfigurable, 130 nm CMOS 108 pJ/pulse, Fully Integrated IR-UWB Receiver for Communication and Precise Ranging

IEEE journal of solid-state circuits, 2010-01, Vol.45 (1), p.69-83

2010

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NBTI model for analogue IC reliability simulation

Electronics letters, 2010-09, Vol.46 (18), p.1279-1280

2010

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The Role of Mobility Degradation in the BTI-Induced RO Aging in a 28-nm Bulk CMOS Technology: (Student paper)

2023 IEEE International Reliability Physics Symposium (IRPS), 2023, p.1-6

2023

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Statistical Characterization of Off-State Stress Degradation in Planar HKMG nFETs Using Device Arrays

2024 IEEE International Reliability Physics Symposium (IRPS), 2024, p.8A.2-1-8A.2-9

2024

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Possible Origins, Identification, and Screening of Silent Data Corruption in Data Centers

2024 IEEE International Reliability Physics Symposium (IRPS), 2024, p.1-7

2024

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Sparse multikernel support vector regression machines trained by active learning

Expert systems with applications, 2012-09, Vol.39 (12), p.11029-11035

2012

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Design of a 2 Mbps FSK near-field transmitter for wireless capsule endoscopy

Sensors and actuators. A. Physical., 2009-11, Vol.156 (1), p.43-48

2009

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A 70 pJ/Pulse Analog Front-End in 130 nm CMOS for UWB Impulse Radio Receivers

IEEE journal of solid-state circuits, 2009-07, Vol.44 (7), p.1862-1871

2009

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Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs

Proceedings of the IEEE, 2007-03, Vol.95 (3), p.640-669

2007

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Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2003-05, Vol.22 (5), p.517-534

2003

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Spherical Wave Based Macromodels for Efficient System-Level EMC Analysis in Circuit Simulators Part I: Optimized Derivation and Truncation Criteria

IEEE transactions on electromagnetic compatibility, 2016-10, Vol.58 (5), p.1494-1505

2016

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Complementary DAC topology for reduced output impedance dependency and improved dynamic performance

Electronics letters, 2012-08, Vol.48 (17), p.1039-1041

2012

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A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS

Efficient and Accurate Statistical Analog Yield Optimization and Variation-Aware Circuit Sizing Based on Computational Intelligence Techniques

An Efficient High-Frequency Linear RF Amplifier Synthesis Method Based on Evolutionary Computation and Machine Learning Techniques

GASPAD: A General and Efficient mm-Wave Integrated Circuit Synthesis Method Based on Surrogate Model Assisted Evolutionary Algorithm

A Low-Complexity Radar Detector Outperforming OS-CFAR for Indoor Drone Obstacle Avoidance

Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy

Synthesis of Integrated Passive Components for High-Frequency RF ICs Based on Evolutionary Computation and Machine Learning Techniques

Improving the Accuracy of Spiking Neural Networks for Radar Gesture Recognition Through Preprocessing

A 3-tier UWB-based indoor localization system for ultra-low-power sensor networks

On the Use of Spiking Neural Networks for Ultralow-Power Radar Gesture Recognition

Analysis and Comparison of Readout Architectures and Analog-to-Digital Converters for 3D-Stacked CMOS Image Sensors

Recurrent sparse support vector regression machines trained by active learning in the time-domain

Assessment of Transistor Aging Models in a 28nm CMOS Technology at a Wide Range of Stress Conditions

A Reconfigurable, 130 nm CMOS 108 pJ/pulse, Fully Integrated IR-UWB Receiver for Communication and Precise Ranging

NBTI model for analogue IC reliability simulation

The Role of Mobility Degradation in the BTI-Induced RO Aging in a 28-nm Bulk CMOS Technology: (Student paper)

Statistical Characterization of Off-State Stress Degradation in Planar HKMG nFETs Using Device Arrays

Possible Origins, Identification, and Screening of Silent Data Corruption in Data Centers

Sparse multikernel support vector regression machines trained by active learning

Design of a 2 Mbps FSK near-field transmitter for wireless capsule endoscopy

A 70 pJ/Pulse Analog Front-End in 130 nm CMOS for UWB Impulse Radio Receivers

Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs

Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits

Spherical Wave Based Macromodels for Efficient System-Level EMC Analysis in Circuit Simulators Part I: Optimized Derivation and Truncation Criteria

Complementary DAC topology for reduced output impedance dependency and improved dynamic performance

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