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Hardware Efficient Low Frequency Artifact Reduction Technique for Wearable ECG Device

IEEE transactions on instrumentation and measurement, 2022, Vol.71, p.1-1

2022

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Machine learning approach for detecting Covid-19 from speech signal using Mel frequency magnitude coefficient

Signal, image and video processing, 2023-09, Vol.17 (6), p.3155-3162

2023

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FPGA Implementation of MRMN with Step-Size Scaler Adaptive Filter for Impulsive Noise Reduction

Circuits, systems, and signal processing, 2020-07, Vol.39 (7), p.3682-3710

2020

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Two Stage Step-Size Scaler Adaptive Filter Design for ECG Denoising

2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, p.1-5

2021

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Design of microfluidic experimental setup for the detection of heavy metal ions using piezoresistive BioMEMS sensor

Microelectronics international, 2020-01, Vol.37 (1), p.10-28

2020

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High-performance hardware architectures for multi-level lifting-based discrete wavelet transform

EURASIP journal on image and video processing, 2014-10, Vol.2014 (1), p.1-19, Article 47

2014

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Interpolated histogram method for area optimised median computation

International journal of electronics, 2013-04, Vol.100 (4), p.468-472

2013

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Implementation of High speed, Low PowerModified Vedic Multiplier and Its Application in Lifting based Discrete Wavelet Transform

TENCON 2019 - 2019 IEEE Region 10 Conference (TENCON), 2019, p.2387-2391

2019

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FPGA-based emulator for functional verification of radio frequency interference mitigation algorithms

2013 Annual IEEE India Conference (INDICON), 2013, p.1-5

2013

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An area efficient and low power implementation of 2048 point FFT/IFFT processor for mobile WiMAX

2010 International Conference on Signal Processing and Communications (SPCOM), 2010, p.1-4

2010

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Hardware Efficient Low Frequency Artifact Reduction Technique for Wearable ECG Device

Machine learning approach for detecting Covid-19 from speech signal using Mel frequency magnitude coefficient

FPGA Implementation of MRMN with Step-Size Scaler Adaptive Filter for Impulsive Noise Reduction

Two Stage Step-Size Scaler Adaptive Filter Design for ECG Denoising

Design of microfluidic experimental setup for the detection of heavy metal ions using piezoresistive BioMEMS sensor

High-performance hardware architectures for multi-level lifting-based discrete wavelet transform

Interpolated histogram method for area optimised median computation

Implementation of High speed, Low PowerModified Vedic Multiplier and Its Application in Lifting based Discrete Wavelet Transform

FPGA-based emulator for functional verification of radio frequency interference mitigation algorithms

An area efficient and low power implementation of 2048 point FFT/IFFT processor for mobile WiMAX

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