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Transient voltage overshoots of high voltage ESD protections based on bipolar transistors in smart power technology

2010 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2010, p.253-256

2010

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Latch-up ring design guidelines to improve electrostatic discharge (ESD) protection scheme efficiency

IEEE journal of solid-state circuits, 2004-10, Vol.39 (10), p.1778-1782

2004

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Analysis and compact modeling of a vertical grounded-base n-p-n bipolar transistor used as ESD protection in a smart power technology

IEEE journal of solid-state circuits, 2001-09, Vol.36 (9), p.1373-1381

2001

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Understanding the Failure Mechanisms of Protection Diodes During System Level ESD: Toward Repetitive Stresses Robustness

IEEE transactions on electron devices, 2012-01, Vol.59 (1), p.108-113

2012

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A System-Level Electrostatic-Discharge-Protection Modeling Methodology for Time-Domain Analysis

IEEE transactions on electromagnetic compatibility, 2013-02, Vol.55 (1), p.45-57

2013

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Efficient TCAD methodology for ESD failure current prediction of smart power ESD protection

Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005, 2005, p.115-118

2005

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Accurate prediction of the ESD robustness of semiconductor devices through physical simulation

2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual, 2005, p.106-111

2005

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The mirrored lateral SCR (MILSCR) as an ESD protection structure: design and optimization using 2-D device simulation

IEEE journal of solid-state circuits, 1999-09, Vol.34 (9), p.1283-1289

1999

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High robustness PNP-based structure for the ESD protection of high voltage I/Os in an advanced smart power technology

2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2007, p.226-229

2007

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ESD stress in RF-MEMS capacitive switches: The influence of dielectric material deposition method

2009 IEEE International Reliability Physics Symposium, 2009, p.568-572

2009

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Pushing away the silicon limits of ESD protection structures: Exploration of crystallographic orientation

2008 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2008, p.200-203

2008

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Analysis and compact modeling of a vertical grounded-base NPN bipolar transistor used as an ESD protection in a smart power technology

Proceedings of the 2000 BIPOLAR/BiCMOS Circuits and Technology Meeting (Cat. No.00CH37124), 2000, p.28-31

2000

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The Mirrored Lateral SCR (MILSCR) as an ESD protection structure for smart power applications

Proceedings of the 1998 Bipolar/BiCMOS Circuits and Technology Meeting (Cat. No.98CH36198), 1998, p.191-194

1998

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Deep Trench NPN Transistor for Low-RON ESD Protection of High-Voltage I/Os in Advanced Smart Power Technology

2006 Bipolar/BiCMOS Circuits and Technology Meeting, 2006, p.1-4

2006

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A Novel Method for Guard Ring Efficiency Assessment and its Applications for ESD Protection Design and Optimization

2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual, 2007, p.606-607

2007

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Geometry effect on power and ESD capability of LDMOS power devices

ISPSD '03. 2003 IEEE 15th International Symposium on Power Semiconductor Devices and ICs, 2003. Proceedings, 2003, p.265-268

2003

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Behavioral-modeling methodology to predict Electrostatic-Discharge susceptibility failures at system level: An IBIS improvement

10th International Symposium on Electromagnetic Compatibility, 2011, p.457-463

2011

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High-temperature operation MOS-IGBT power clamp for improved ESD protection in smart power SOI technology

EOS/ESD Symposium Proceedings, 2011, p.1-8

2011

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TCAD and SPICE modeling help solve ESD protection issues in analog CMOS technology

2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595), 2002, Vol.2, p.749-752 vol.2

2002

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Investigation of statistical tools to analyze repetitive HMM stress endurance of system-level ESD protection

EOS/ESD Symposium Proceedings, 2011, p.1-9

2011

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Investigating the probability of susceptibility failure within ESD system level consideration

EOS/ESD Symposium Proceedings, 2011, p.1-6

2011

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TCAD Methodology for ESD Robustness Prediction of Smart Power ESD Devices

IEEE transactions on device and materials reliability, 2006-09, Vol.6 (3), p.399-407

2006

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Local ESD protection structure based on silicon controlled rectifier achieving very low overshoot voltage

2009 31st EOS/ESD Symposium, 2009, p.1-8

2009

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Area-efficient, reduced and no-snapback PNP-based ESD protection in advanced Smart Power technology

2006 Electrical Overstress/Electrostatic Discharge Symposium, 2006, p.69-76

2006

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Characterization and modeling methodology for IC's ESD susceptibility at system level using VF-TLP tester

2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2007, p.5B.1-1-5B.1-7

2007

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Transient voltage overshoots of high voltage ESD protections based on bipolar transistors in smart power technology

Latch-up ring design guidelines to improve electrostatic discharge (ESD) protection scheme efficiency

Analysis and compact modeling of a vertical grounded-base n-p-n bipolar transistor used as ESD protection in a smart power technology

Understanding the Failure Mechanisms of Protection Diodes During System Level ESD: Toward Repetitive Stresses Robustness

A System-Level Electrostatic-Discharge-Protection Modeling Methodology for Time-Domain Analysis

Efficient TCAD methodology for ESD failure current prediction of smart power ESD protection

Accurate prediction of the ESD robustness of semiconductor devices through physical simulation

The mirrored lateral SCR (MILSCR) as an ESD protection structure: design and optimization using 2-D device simulation

High robustness PNP-based structure for the ESD protection of high voltage I/Os in an advanced smart power technology

ESD stress in RF-MEMS capacitive switches: The influence of dielectric material deposition method

Pushing away the silicon limits of ESD protection structures: Exploration of crystallographic orientation

Analysis and compact modeling of a vertical grounded-base NPN bipolar transistor used as an ESD protection in a smart power technology

The Mirrored Lateral SCR (MILSCR) as an ESD protection structure for smart power applications

Deep Trench NPN Transistor for Low-RON ESD Protection of High-Voltage I/Os in Advanced Smart Power Technology

A Novel Method for Guard Ring Efficiency Assessment and its Applications for ESD Protection Design and Optimization

Geometry effect on power and ESD capability of LDMOS power devices

Behavioral-modeling methodology to predict Electrostatic-Discharge susceptibility failures at system level: An IBIS improvement

High-temperature operation MOS-IGBT power clamp for improved ESD protection in smart power SOI technology

TCAD and SPICE modeling help solve ESD protection issues in analog CMOS technology

Investigation of statistical tools to analyze repetitive HMM stress endurance of system-level ESD protection

Investigating the probability of susceptibility failure within ESD system level consideration

TCAD Methodology for ESD Robustness Prediction of Smart Power ESD Devices

Local ESD protection structure based on silicon controlled rectifier achieving very low overshoot voltage

Area-efficient, reduced and no-snapback PNP-based ESD protection in advanced Smart Power technology

Characterization and modeling methodology for IC's ESD susceptibility at system level using VF-TLP tester

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