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Silicon Millimeter-Wave, Terahertz, and High-Speed Fiber-Optic Device and Benchmark Circuit Scaling Through the 2030 ITRS Horizon

Proceedings of the IEEE, 2017-06, Vol.105 (6), p.1087-1104

2017

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Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology

IEEE transactions on circuits and systems. I, Regular papers, 2017-04, Vol.64 (4), p.847-857

2017

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A TCAD-Based Analysis of Substrate Bias Effect on Asymmetric Lateral SiGe HBT for THz Applications

IEEE transactions on electron devices, 2023-05, Vol.70 (5), p.1-7

2023

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Improved Thermal Performance of SOI Using a Compound Buried Layer

IEEE transactions on electron devices, 2014-06, Vol.61 (6), p.1999-2006

2014

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Heterogeneous Silicon Photonic Integrated Circuits

Journal of lightwave technology, 2016-01, Vol.34 (1), p.20-35

2016

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Modulation of post-fracture roughness with induced shear stress in the smart cut process

Journal of applied physics, 2024-07, Vol.136 (4)

2024

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Considerations for Ultimate CMOS Scaling

IEEE transactions on electron devices, 2012-07, Vol.59 (7), p.1813-1828

Kuhn, K. J.

2012

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Impact strain engineering on gate stack quality and reliability

Solid-state electronics, 2008-08, Vol.52 (8), p.1115-1126

2008

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Methodology for parameters extraction with undoped junctionless EZ-FETs

Solid-state electronics, 2024-07, Vol.217, p.108897, Article 108897

2024

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Experimental Comparison Between Trigate p-TFET and p-FinFET Analog Performance as a Function of Temperature

IEEE transactions on electron devices, 2013-08, Vol.60 (8), p.2493-2497

2013

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Silicon Photonic Circuits: On-CMOS Integration, Fiber Optical Coupling, and Packaging

IEEE journal of selected topics in quantum electronics, 2011-05, Vol.17 (3), p.498-509

2011

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Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

Solid-state electronics, 2024-04, Vol.214, p.108865, Article 108865

2024

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Ultrathin Crystalline Silicon Nano and Micro Membranes with High Areal Density for Low-Cost Flexible Electronics

Small (Weinheim an der Bergstrasse, Germany), 2023-09, Vol.19 (39), p.e2302597-e2302597

2023

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Bipolar Charge-Plasma Transistor: A Novel Three Terminal Device

IEEE transactions on electron devices, 2012-04, Vol.59 (4), p.962-967

2012

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Optimized Silicon AWG With Flattened Spectral Response Using an MMI Aperture

Journal of lightwave technology, 2013-01, Vol.31 (1), p.87-93

2013

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Editorial Editorial Introduction to JSTQE Special Issue on Photonic Electronic Co-Integration and Advanced Transfer Printing

IEEE journal of selected topics in quantum electronics, 2023-05, Vol.29 (3: Photon. Elec. Co-Inte. and Adv. Trans. Print.), p.3-6

2023

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A High-Temperature SiC Three-Phase AC-DC Converter Design for > 100 °C Ambient Temperature

IEEE transactions on power electronics, 2013, Vol.28 (1), p.555-572

2013

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Low-subthreshold-swing tunnel transistors

IEEE electron device letters, 2006-04, Vol.27 (4), p.297-300

2006

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Correlation of Scattering Loss, Sidewall Roughness and Waveguide Width in Silicon-on-Insulator (SOI) Ridge Waveguides

Journal of lightwave technology, 2009-09, Vol.27 (18), p.3999-4008

2009

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Scalability of Extremely Thin SOI (ETSOI) MOSFETs to Sub-20-nm Gate Length

IEEE electron device letters, 2012-02, Vol.33 (2), p.149-151

2012

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Comprehensive Analysis of Short-Channel Effects in Ultrathin SOI MOSFETs

IEEE transactions on electron devices, 2013-06, Vol.60 (6), p.1814-1819

2013

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Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor

IEEE journal of solid-state circuits, 2006-01, Vol.41 (1), p.179-196

2006

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A Linear High-Power Reconfigurable SOI-CMOS Front-End Module for WI-FI 6/6E Applications

2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2022, p.39-42

2022

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New High-Voltage ( > 1200 V) MOSFET With the Charge Trenches on Partial SOI

IEEE transactions on electron devices, 2008-07, Vol.55 (7), p.1756-1761

2008

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TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model

Microelectronic engineering, 2012-10, Vol.98, p.334-337

2012

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Silicon Millimeter-Wave, Terahertz, and High-Speed Fiber-Optic Device and Benchmark Circuit Scaling Through the 2030 ITRS Horizon

Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology

A TCAD-Based Analysis of Substrate Bias Effect on Asymmetric Lateral SiGe HBT for THz Applications

Improved Thermal Performance of SOI Using a Compound Buried Layer

Heterogeneous Silicon Photonic Integrated Circuits

Modulation of post-fracture roughness with induced shear stress in the smart cut process

Considerations for Ultimate CMOS Scaling

Impact strain engineering on gate stack quality and reliability

Methodology for parameters extraction with undoped junctionless EZ-FETs

Experimental Comparison Between Trigate p-TFET and p-FinFET Analog Performance as a Function of Temperature

Silicon Photonic Circuits: On-CMOS Integration, Fiber Optical Coupling, and Packaging

Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

Ultrathin Crystalline Silicon Nano and Micro Membranes with High Areal Density for Low-Cost Flexible Electronics

Bipolar Charge-Plasma Transistor: A Novel Three Terminal Device

Optimized Silicon AWG With Flattened Spectral Response Using an MMI Aperture

Editorial Editorial Introduction to JSTQE Special Issue on Photonic Electronic Co-Integration and Advanced Transfer Printing

A High-Temperature SiC Three-Phase AC-DC Converter Design for > 100 °C Ambient Temperature

Low-subthreshold-swing tunnel transistors

Correlation of Scattering Loss, Sidewall Roughness and Waveguide Width in Silicon-on-Insulator (SOI) Ridge Waveguides

Scalability of Extremely Thin SOI (ETSOI) MOSFETs to Sub-20-nm Gate Length

Comprehensive Analysis of Short-Channel Effects in Ultrathin SOI MOSFETs

Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor

A Linear High-Power Reconfigurable SOI-CMOS Front-End Module for WI-FI 6/6E Applications

New High-Voltage ( > 1200 V) MOSFET With the Charge Trenches on Partial SOI

TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model

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