UB Paderborn / Katalog / Suche / in CDI

1 – 23 von 23

Sortiert nach

System ESD robustness by co-design of on-chip and on-board protection measures

Microelectronics and reliability, 2010-09, Vol.50 (9), p.1359-1366

2010

Volltextzugriff (PDF)

Characterization and Optimization of Sub-32-nm FinFET Devices for ESD Applications

IEEE transactions on electron devices, 2008-12, Vol.55 (12), p.3507-3516

2008

Volltextzugriff (PDF)

Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures

IEEE transactions on electron devices, 2012-05, Vol.59 (5), p.1353-1363

2012

Volltextzugriff (PDF)

A Novel Drain-Extended FinFET Device for High-Voltage High-Speed Applications

IEEE electron device letters, 2012-10, Vol.33 (10), p.1432-1434

2012

Volltextzugriff (PDF)

A Drain-Extended MOS Device With Spreading Filament Under ESD Stress

IEEE electron device letters, 2012-09, Vol.33 (9), p.1294-1296

2012

Volltextzugriff (PDF)

Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices

IEEE transactions on electron devices, 2010-02, Vol.57 (2), p.448-457

2010

Volltextzugriff (PDF)

RF ESD protection strategies: Codesign vs. low- C protection

Microelectronics and reliability, 2007-07, Vol.47 (7), p.1008-1015

2007

Volltextzugriff (PDF)

Toward System on Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines

IEEE transactions on electron devices, 2011-06, Vol.58 (6), p.1597-1607

2011

Volltextzugriff (PDF)

Part I: On the Behavior of STI-Type DeNMOS Device Under ESD Conditions

IEEE transactions on electron devices, 2010-09, Vol.57 (9), p.2235-2242

2010

Volltextzugriff (PDF)

Part II: On the Three-Dimensional Filamentation and Failure Modeling of STI Type DeNMOS Device Under Various ESD Conditions

IEEE transactions on electron devices, 2010-09, Vol.57 (9), p.2243-2250

2010

Volltextzugriff (PDF)

An Insight Into the ESD Behavior of the Nanometer-Scale Drain-Extended NMOS Device-Part I: Turn-On Behavior of the Parasitic Bipolar

IEEE transactions on electron devices, 2011-02, Vol.58 (2), p.309-317

2011

Volltextzugriff (PDF)

An Insight Into ESD Behavior of Nanometer-Scale Drain Extended NMOS (DeNMOS) Devices: Part II (Two-Dimensional Study-Biasing & Comparison With NMOS)

IEEE transactions on electron devices, 2011-02, Vol.58 (2), p.318-326

2011

Volltextzugriff (PDF)

High abstraction level permutational ESD concept analysis

Microelectronics and reliability, 2005-02, Vol.45 (2), p.313-321

2005

Volltextzugriff (PDF)

Part II: A Novel Scheme to Optimize the Mixed-Signal Performance and Hot-carrier Reliability of Drain-Extended MOS Devices

IEEE transactions on electron devices, 2010-02, Vol.57 (2), p.458-465

2010

Volltextzugriff (PDF)

Dangerous parasitics of socketed CDM ESD testers

Microelectronics and reliability, 1997-10, Vol.37 (10), p.1465-1468

1997

Volltextzugriff (PDF)

Base pushout driven snapback in parasitic bipolar devices between different power domains

2004 IEEE International Reliability Physics Symposium. Proceedings, 2004, p.387-392

2004

Volltextzugriff (PDF)

Influence of self-assembling growth on the shape and the orientation of silicon nanostructures

Journal of crystal growth, 1995-12, Vol.157 (1), p.308-311

1995

Volltextzugriff (PDF)

A Dedicated TLP Set-Up to Investigate the ESD Robustness of RF Elements and Circuits

Microelectronics and reliability, 2005-09, Vol.45 (9), p.1421-1424

2005

Volltextzugriff (PDF)

Chip-level ESD simulation for fail detection and design guidance

2004 IEEE International Reliability Physics Symposium. Proceedings, 2004, p.603-604

2004

Volltextzugriff (PDF)

Fabrication and characterization of Si/SiGe nanometer structures

Microelectronic engineering, 1995-02, Vol.27 (1), p.83-86

1995

Volltextzugriff (PDF)

Fabrication and characterisation of locally grown SiGe wires and dots

Materials science and technology, 1995-04, Vol.11 (4), p.407-409

1995

Volltextzugriff (PDF)

Vertical MOS technology with sub-0.1μm channel lengths

Electronics letters, 1995-08, Vol.31 (16), p.1394-1395

1995

Volltextzugriff (PDF)

ESD protection for the deep sub micron regime - a challenge for design methodology

17th International Conference on VLSI Design. Proceedings, 2004, p.809-818

Gossner, H.

2004

Volltextzugriff (PDF)

1 – 23 von 23

Suche als RSS-Feed

Aktive Filter

ThemaElectronics

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(20)
Mit Volltextzugriff
(21)

Publikationsform

Artikel
(20)
Tagungsberichte
(3)

Sprache

Englisch
(23)
Japanisch
(1)

Erscheinungsjahr

n.n

Zeitschrift / Serie

2 weitere anzeigen...

Weniger anzeigen...

Menü

Weitere Dienste

Einstellungen

System ESD robustness by co-design of on-chip and on-board protection measures

Characterization and Optimization of Sub-32-nm FinFET Devices for ESD Applications

Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures

A Novel Drain-Extended FinFET Device for High-Voltage High-Speed Applications

A Drain-Extended MOS Device With Spreading Filament Under ESD Stress

Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices

RF ESD protection strategies: Codesign vs. low- C protection

Toward System on Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines

Part I: On the Behavior of STI-Type DeNMOS Device Under ESD Conditions

Part II: On the Three-Dimensional Filamentation and Failure Modeling of STI Type DeNMOS Device Under Various ESD Conditions

An Insight Into the ESD Behavior of the Nanometer-Scale Drain-Extended NMOS Device-Part I: Turn-On Behavior of the Parasitic Bipolar

An Insight Into ESD Behavior of Nanometer-Scale Drain Extended NMOS (DeNMOS) Devices: Part II (Two-Dimensional Study-Biasing & Comparison With NMOS)

High abstraction level permutational ESD concept analysis

Part II: A Novel Scheme to Optimize the Mixed-Signal Performance and Hot-carrier Reliability of Drain-Extended MOS Devices

Dangerous parasitics of socketed CDM ESD testers

Base pushout driven snapback in parasitic bipolar devices between different power domains

Influence of self-assembling growth on the shape and the orientation of silicon nanostructures

A Dedicated TLP Set-Up to Investigate the ESD Robustness of RF Elements and Circuits

Chip-level ESD simulation for fail detection and design guidance

Fabrication and characterization of Si/SiGe nanometer structures

Fabrication and characterisation of locally grown SiGe wires and dots

Vertical MOS technology with sub-0.1μm channel lengths

ESD protection for the deep sub micron regime - a challenge for design methodology

Aktive Filter

Suchergebnisse filtern