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Fast Strategies for the Implementation of SIKE Round 3 on ARM Cortex-M4

IEEE transactions on circuits and systems. I, Regular papers, 2021-10, Vol.68 (10), p.4129-4141

2021

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Efficient Error Detection Architectures for Postquantum Signature Falcon's Sampler and KEM SABER

IEEE transactions on very large scale integration (VLSI) systems, 2022-06, Vol.30 (6), p.794-802

2022

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A High-Performance and Scalable Hardware Architecture for Isogeny-Based Cryptography

IEEE transactions on computers, 2018-11, Vol.67 (11), p.1594-1609

2018

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Efficient Error Detection Cryptographic Architectures Benchmarked on FPGAs for Montgomery Ladder

IEEE transactions on very large scale integration (VLSI) systems, 2024-11, Vol.32 (11), p.2154-2158

2024

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Hardware Constructions for Error Detection in Lightweight Authenticated Cipher ASCON Benchmarked on FPGA

IEEE transactions on circuits and systems. II, Express briefs, 2022-04, Vol.69 (4), p.2276-2280

2022

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Instruction-Set Accelerated Implementation of CRYSTALS-Kyber

IEEE transactions on circuits and systems. I, Regular papers, 2021-11, Vol.68 (11), p.4648-4659

2021

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Cryptographic Accelerators for Digital Signature Based on Ed25519

IEEE transactions on very large scale integration (VLSI) systems, 2021-07, Vol.29 (7), p.1297-1305

2021

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High-Speed NTT-based Polynomial Multiplication Accelerator for Post-Quantum Cryptography

2021 IEEE 28th Symposium on Computer Arithmetic (ARITH), 2021, p.94-101

2021

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Reliable Architecture-Oblivious Error Detection Schemes for Secure Cryptographic GCM Structures

IEEE transactions on reliability, 2019-12, Vol.68 (4), p.1347-1355

2019

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CRC-Based Error Detection Constructions for FLT and ITA Finite Field Inversions Over GF(2m)

IEEE transactions on very large scale integration (VLSI) systems, 2021-05, Vol.29 (5), p.1033-1037

2021

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Reliable Architectures for Finite Field Multipliers Using Cyclic Codes on FPGA Utilized in Classic and Post-Quantum Cryptography

IEEE transactions on very large scale integration (VLSI) systems, 2023-01, Vol.31 (1), p.157-161

2023

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Hardware Constructions for Error Detection in Lightweight Welch-Gong (WG)-Oriented Streamcipher WAGE Benchmarked on FPGA

IEEE transactions on emerging topics in computing, 2022-04, Vol.10 (2), p.1208-1215

2022

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Hardware Constructions for Lightweight Cryptographic Block Cipher QARMA With Error Detection Mechanisms

IEEE transactions on emerging topics in computing, 2022-01, Vol.10 (1), p.514-519

2022

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ARMv8 SIKE: Optimized Supersingular Isogeny Key Encapsulation on ARMv8 Processors

IEEE transactions on circuits and systems. I, Regular papers, 2019-11, Vol.66 (11), p.4209-4218

2019

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Efficient Error Detection Schemes for ECSM Window Method Benchmarked on FPGAs

IEEE transactions on very large scale integration (VLSI) systems, 2024-03, Vol.32 (3), p.592-596

2024

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Accelerated RISC-V for Post-Quantum SIKE

IEEE transactions on circuits and systems. I, Regular papers, 2022-06, Vol.69 (6), p.2490-2501

2022

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Reliable Hardware Architectures for Cryptographic Block Ciphers LED and HIGHT

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-10, Vol.36 (10), p.1750-1758

2017

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Efficient and Side-Channel Resistant Ed25519 on ARM Cortex-M4

IEEE transactions on circuits and systems. I, Regular papers, 2024-06, Vol.71 (6), p.2674-2686

2024

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Hardware Constructions for Error Detection of Number-Theoretic Transform Utilized in Secure Cryptographic Architectures

IEEE transactions on very large scale integration (VLSI) systems, 2019-03, Vol.27 (3), p.738-741

2019

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Error Detection Schemes Assessed on FPGA for Multipliers in Lattice-Based Key Encapsulation Mechanisms in Post-Quantum Cryptography

IEEE transactions on emerging topics in computing, 2023-07, Vol.11 (3), p.1-6

2023

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Area-Time Efficient Hardware Architecture for Signature Based on Ed448

IEEE transactions on circuits and systems. II, Express briefs, 2021-08, Vol.68 (8), p.2942-2946

2021

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Reliable Architectures for Composite-Field-Oriented Constructions of McEliece Post-Quantum Cryptography on FPGA

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-05, Vol.40 (5), p.999-1003

2021

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Error Detection Architectures for Ring Polynomial Multiplication and Modular Reduction of Ring-LWE in [Formula Omitted] Benchmarked on ASIC

IEEE transactions on reliability, 2021-03, Vol.70 (1), p.362

2021

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Dual-Basis Superserial Multipliers for Secure Applications and Lightweight Cryptographic Architectures

IEEE transactions on circuits and systems. II, Express briefs, 2014-02, Vol.61 (2), p.125-129

2014

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Error Detection Constructions for ITA Finite Field Inversions Over [Formula Omitted] on FPGA Using CRC and Hamming Codes

IEEE transactions on reliability, 2023-06, Vol.72 (2), p.651

2023

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Fast Strategies for the Implementation of SIKE Round 3 on ARM Cortex-M4

Efficient Error Detection Architectures for Postquantum Signature Falcon's Sampler and KEM SABER

A High-Performance and Scalable Hardware Architecture for Isogeny-Based Cryptography

Efficient Error Detection Cryptographic Architectures Benchmarked on FPGAs for Montgomery Ladder

Hardware Constructions for Error Detection in Lightweight Authenticated Cipher ASCON Benchmarked on FPGA

Instruction-Set Accelerated Implementation of CRYSTALS-Kyber

Cryptographic Accelerators for Digital Signature Based on Ed25519

High-Speed NTT-based Polynomial Multiplication Accelerator for Post-Quantum Cryptography

Reliable Architecture-Oblivious Error Detection Schemes for Secure Cryptographic GCM Structures

CRC-Based Error Detection Constructions for FLT and ITA Finite Field Inversions Over GF(2m)

Reliable Architectures for Finite Field Multipliers Using Cyclic Codes on FPGA Utilized in Classic and Post-Quantum Cryptography

Hardware Constructions for Error Detection in Lightweight Welch-Gong (WG)-Oriented Streamcipher WAGE Benchmarked on FPGA

Hardware Constructions for Lightweight Cryptographic Block Cipher QARMA With Error Detection Mechanisms

ARMv8 SIKE: Optimized Supersingular Isogeny Key Encapsulation on ARMv8 Processors

Efficient Error Detection Schemes for ECSM Window Method Benchmarked on FPGAs

Accelerated RISC-V for Post-Quantum SIKE

Reliable Hardware Architectures for Cryptographic Block Ciphers LED and HIGHT

Efficient and Side-Channel Resistant Ed25519 on ARM Cortex-M4

Hardware Constructions for Error Detection of Number-Theoretic Transform Utilized in Secure Cryptographic Architectures

Error Detection Schemes Assessed on FPGA for Multipliers in Lattice-Based Key Encapsulation Mechanisms in Post-Quantum Cryptography

Area-Time Efficient Hardware Architecture for Signature Based on Ed448

Reliable Architectures for Composite-Field-Oriented Constructions of McEliece Post-Quantum Cryptography on FPGA

Error Detection Architectures for Ring Polynomial Multiplication and Modular Reduction of Ring-LWE in [Formula Omitted] Benchmarked on ASIC

Dual-Basis Superserial Multipliers for Secure Applications and Lightweight Cryptographic Architectures

Error Detection Constructions for ITA Finite Field Inversions Over [Formula Omitted] on FPGA Using CRC and Hamming Codes

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