UB Paderborn / Katalog / Suche / in CDI

Best-effort computing: re-thinking parallel software and hardware

Design Automation Conference, 2010, p.865-870

2010

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Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency

Design Automation Conference, 2010, p.555-560

2010

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An Energy-Efficient Heterogeneous System for Embedded Learning and Classification

IEEE embedded systems letters, 2011-03, Vol.3 (1), p.42-45

2011

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Computing approximately, and efficiently

2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, p.748-751

2015

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Approximate computing: An integrated hardware approach

2013 Asilomar Conference on Signals, Systems and Computers, 2013, p.111-117

2013

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Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-10, Vol.25 (10), p.2193-2206

2006

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Approximate computing for efficient information processing

2014 IEEE 12th Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia), 2014, p.9-10

2014

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A test function architecture for interconnected finite state machines

Proceedings of 7th International Conference on VLSI Design, 1994, p.113-116

1994

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Cypress: compression and encryption of data and code for embedded multimedia systems

IEEE design & test of computers, 2004-09, Vol.21 (5), p.406-415

2004

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A programmable parallel accelerator for learning and classification

2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2010, p.273-284

2010

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Dynamic effort scaling: managing the quality-efficiency tradeoff

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 2011, p.603-608

2011

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A methodology for design, modeling, and analysis of networks-on-chip

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.1778-1781 Vol. 2

2005

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A case study in networks-on-chip design for embedded video

Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004, Vol.2, p.770-775 Vol.2

2004

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A Massively Parallel FPGA-Based Coprocessor for Support Vector Machines

2009 17th IEEE Symposium on Field Programmable Custom Computing Machines, 2009, p.115-122

2009

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HERMES: A Software Architecture for Visibility and Control in Wireless Sensor Network Deployments

2008 International Conference on Information Processing in Sensor Networks (ipsn 2008), 2008, p.395-406

2008

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Best-effort computing: re-thinking parallel software and hardware

Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency

An Energy-Efficient Heterogeneous System for Embedded Learning and Classification

Computing approximately, and efficiently

Approximate computing: An integrated hardware approach

Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques

Approximate computing for efficient information processing

A test function architecture for interconnected finite state machines

Cypress: compression and encryption of data and code for embedded multimedia systems

A programmable parallel accelerator for learning and classification

Dynamic effort scaling: managing the quality-efficiency tradeoff

A methodology for design, modeling, and analysis of networks-on-chip

A case study in networks-on-chip design for embedded video

A Massively Parallel FPGA-Based Coprocessor for Support Vector Machines

HERMES: A Software Architecture for Visibility and Control in Wireless Sensor Network Deployments

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