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A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors

IEEE transactions on very large scale integration (VLSI) systems, 2011-05, Vol.19 (5), p.900-904

2011

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Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems

IEEE transactions on instrumentation and measurement, 2010-05, Vol.59 (5), p.1127-1133

2010

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A novel CNTFET-based ternary logic gate design

2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009, p.435-438

2009

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A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems

IEEE transactions on very large scale integration (VLSI) systems, 2009-04, Vol.17 (4), p.517-528

2009

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A Novel Statistical Timing and Leakage Power Characterization of Partially Depleted Silicon-on-Insulator Gates

IEEE transactions on instrumentation and measurement, 2009-02, Vol.58 (2), p.401-410

2009

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A Tunable High-Gain Low-Noise Transimpedance Amplifier for Biosensing

2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), 2020, p.1007-1010

2020

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Fault Tolerant Source Routing for Network-on-chip

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007, p.12-20

2007

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Assessment of CNTFET based circuit performance and robustness to PVT variations

2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009, p.1106-1109

2009

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Soft-Error Hardening Designs of Nanoscale CMOS Latches

2009 27th IEEE VLSI Test Symposium, 2009, p.41-46

2009

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A Time-Domain Parallel Counter for Deep Learning Macro

2022 19th International SoC Design Conference (ISOCC), 2022, p.346-347

2022

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A novel design technique for soft error hardening of Nanoscale CMOS memory

2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009, p.679-682

2009

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A Novel Hardened Design of a CMOS Memory Cell at 32nm

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009, p.58-64

2009

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A Compensation Technique for Threshold Mismatch in Sub-threshold Current Mirror

2021 IEEE Microelectronics Design & Test Symposium (MDTS), 2021, p.1-4

2021

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A low power 100MΩ CMOS front-end transimpedance amplifier for biosensing applications

2010 53rd IEEE International Midwest Symposium on Circuits and Systems, 2010, p.541-544

2010

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A 100MS/s 10-bit Split-SAR ADC with Capacitor Mismatch Compensation Using Built-In Calibration

2016 IEEE 25th North Atlantic Test Workshop (NATW), 2016, p.1-5

2016

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Optimal Body Biasing for Minimum Leakage Power in Standby Mode

2007 IEEE International Symposium on Circuits and Systems (ISCAS), 2007, p.1161-1164

2007

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A new SRAM cell design using CNTFETs

2008 International SoC Design Conference, 2008, Vol.1, p.I-168-I-171

2008

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Optimization of Null Convenction Logic Using Gate Diffusion Input

2019 International SoC Design Conference (ISOCC), 2019, p.21-22

2019

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Area Efficient Multi-Threshold Null Convenction Logic

2019 International SoC Design Conference (ISOCC), 2019, p.27-28

2019

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A 4Gb/s half-rate DFE with switched-cap and IIR summation for data correction

2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, p.1-4

2017

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A low power 8T SRAM cell design technique for CNFET

2008 International SoC Design Conference, 2008, Vol.1, p.I-176-I-179

2008

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Leakage Minimization Technique for Nanoscale CMOS VLSI

IEEE design & test of computers, 2007-07, Vol.24 (4), p.322-330

2007

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Probabilistic leakage power estimation of Partially-Depleted Silicon-On-Insulator (SOI) gates

2007 50th Midwest Symposium on Circuits and Systems, 2007, p.980-983

2007

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A novel all-digital fractional-N frequency synthesizer architecture with fast acquisition and low spur

2010 11th International Symposium on Quality Electronic Design (ISQED), 2010, p.99-102

2010

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A low power CMOS CORDIC processor design for wireless telecommunication

2007 50th Midwest Symposium on Circuits and Systems, 2007, p.1336-1339

2007

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A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors

Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems

A novel CNTFET-based ternary logic gate design

A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems

A Novel Statistical Timing and Leakage Power Characterization of Partially Depleted Silicon-on-Insulator Gates

A Tunable High-Gain Low-Noise Transimpedance Amplifier for Biosensing

Fault Tolerant Source Routing for Network-on-chip

Assessment of CNTFET based circuit performance and robustness to PVT variations

Soft-Error Hardening Designs of Nanoscale CMOS Latches

A Time-Domain Parallel Counter for Deep Learning Macro

A novel design technique for soft error hardening of Nanoscale CMOS memory

A Novel Hardened Design of a CMOS Memory Cell at 32nm

A Compensation Technique for Threshold Mismatch in Sub-threshold Current Mirror

A low power 100MΩ CMOS front-end transimpedance amplifier for biosensing applications

A 100MS/s 10-bit Split-SAR ADC with Capacitor Mismatch Compensation Using Built-In Calibration

Optimal Body Biasing for Minimum Leakage Power in Standby Mode

A new SRAM cell design using CNTFETs

Optimization of Null Convenction Logic Using Gate Diffusion Input

Area Efficient Multi-Threshold Null Convenction Logic

A 4Gb/s half-rate DFE with switched-cap and IIR summation for data correction

A low power 8T SRAM cell design technique for CNFET

Leakage Minimization Technique for Nanoscale CMOS VLSI

Probabilistic leakage power estimation of Partially-Depleted Silicon-On-Insulator (SOI) gates

A novel all-digital fractional-N frequency synthesizer architecture with fast acquisition and low spur

A low power CMOS CORDIC processor design for wireless telecommunication

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