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A Two-Stage Interpolation Time-to-Digital Converter Implemented in 20 and 28 nm FGPAs

IEEE transactions on industrial electronics (1982), 2024-11, Vol.71 (11), p.15200-15210

2024

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Low-Hardware Consumption, Resolution-Configurable Gray Code Oscillator Time-to-Digital Converters Implemented in 16 nm, 20 nm, and 28 nm FPGAs

IEEE transactions on industrial electronics (1982), 2023-04, Vol.70 (4), p.4256-4266

2023

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Timing Characterization for Static Timing Analysis of Single Flux Quantum Circuits

IEEE transactions on applied superconductivity, 2019-09, Vol.29 (6), p.1-8

2019

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A Novel Design Method for Resolver-to-Digital Conversion

IEEE transactions on industrial electronics (1982), 2015-06, Vol.62 (6), p.3724-3731

2015

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Reducing LUT Count for Mealy FSMs With Transformation of States

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-05, Vol.41 (5), p.1400-1411

2022

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Area-Efficient Intellectual Property (IP) Design of Advanced Encryption Standard

IEEE transactions on circuits and systems. II, Express briefs, 2023-10, Vol.70 (10), p.1-1

2023

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Low-Area and High-Throughput Architecture for an Adaptive Filter Using Distributed Arithmetic

IEEE transactions on circuits and systems. II, Express briefs, 2013-11, Vol.60 (11), p.781-785

2013

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Design and Implementation of SRAM for LUT and CLB Using Clocking Mechanism in Quantum-Dot Cellular Automata

IEEE transactions on circuits and systems. II, Express briefs, 2022-09, Vol.69 (9), p.3909-3913

2022

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A Memory-Based Direct-Digital Frequency Synthesizer for Fractional Synchronization

IEEE transactions on circuits and systems. II, Express briefs, 2022-03, Vol.69 (3), p.899-903

2022

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Development of an All-SFQ Superconducting Field-Programmable Gate Array

IEEE transactions on applied superconductivity, 2019-06, Vol.29 (4), p.1-12

2019

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Design and Implementation of an Ultralow-Energy FFT ASIC for Processing ECG in Cardiac Pacemakers

IEEE transactions on very large scale integration (VLSI) systems, 2019-04, Vol.27 (4), p.983-987

2019

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A 2.2-GHz Configurable Direct Digital Frequency Synthesizer Based on LUT and Rotation

IEEE transactions on circuits and systems. I, Regular papers, 2019-05, Vol.66 (5), p.1970-1980

2019

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A Single-Chip 64-Channel Ultrasound RX-Beamformer Including Analog Front-End and an LUT for Non-Uniform ADC-Sample-Clock Generation

IEEE transactions on biomedical circuits and systems, 2017-02, Vol.11 (1), p.87-97

2017

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A 640-Mb/s 2048-bit programmable LDPC decoder chip

IEEE journal of solid-state circuits, 2006-03, Vol.41 (3), p.684-698

2006

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Improving characteristics of LUT-based Moore FSMs

IEEE access, 2020-01, Vol.8, p.1-1

2020

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Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed

IEEE transactions on very large scale integration (VLSI) systems, 2013-05, Vol.21 (5), p.901-909

2013

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A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating

IEEE transactions on very large scale integration (VLSI) systems, 2011-08, Vol.19 (8), p.1394-1406

2011

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Multi-Electrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-09, p.1-1

2023

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A 630 MHz, 76 mW Direct Digital Frequency Synthesizer Using Enhanced ROM Compression Technique

IEEE journal of solid-state circuits, 2007-02, Vol.42 (2), p.350-360

2007

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A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations

IEEE transactions on circuits and systems. II, Express briefs, 2024-06, p.1-1

2024

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FPGA-Based True Random Number Generation Using Programmable Delays in Oscillator-Rings

IEEE transactions on circuits and systems. II, Express briefs, 2020-03, Vol.67 (3), p.570-574

2020

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Design of a Common High-Performance Data Acquisition System for Physics Experiments at HIAF

IEEE transactions on nuclear science, 2024-10, p.1-1

2024

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A General Framework for FPGA-Based Real-Time Emulation of Electrical Machines for HIL Applications

IEEE transactions on industrial electronics (1982), 2015-04, Vol.62 (4), p.2041-2053

2015

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Efficient Time-to-Digital Converters in 20 nm FPGAs With Wave Union Methods

IEEE transactions on industrial electronics (1982), 2022-01, Vol.69 (1), p.1021-1031

2022

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FPGA-based fast image warping with data-parallelization schemes

IEEE transactions on consumer electronics, 2008-11, Vol.54 (4), p.2053-2059

2008

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A Two-Stage Interpolation Time-to-Digital Converter Implemented in 20 and 28 nm FGPAs

Low-Hardware Consumption, Resolution-Configurable Gray Code Oscillator Time-to-Digital Converters Implemented in 16 nm, 20 nm, and 28 nm FPGAs

Timing Characterization for Static Timing Analysis of Single Flux Quantum Circuits

A Novel Design Method for Resolver-to-Digital Conversion

Reducing LUT Count for Mealy FSMs With Transformation of States

Area-Efficient Intellectual Property (IP) Design of Advanced Encryption Standard

Low-Area and High-Throughput Architecture for an Adaptive Filter Using Distributed Arithmetic

Design and Implementation of SRAM for LUT and CLB Using Clocking Mechanism in Quantum-Dot Cellular Automata

A Memory-Based Direct-Digital Frequency Synthesizer for Fractional Synchronization

Development of an All-SFQ Superconducting Field-Programmable Gate Array

Design and Implementation of an Ultralow-Energy FFT ASIC for Processing ECG in Cardiac Pacemakers

A 2.2-GHz Configurable Direct Digital Frequency Synthesizer Based on LUT and Rotation

A Single-Chip 64-Channel Ultrasound RX-Beamformer Including Analog Front-End and an LUT for Non-Uniform ADC-Sample-Clock Generation

A 640-Mb/s 2048-bit programmable LDPC decoder chip

Improving characteristics of LUT-based Moore FSMs

Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed

A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating

Multi-Electrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization

A 630 MHz, 76 mW Direct Digital Frequency Synthesizer Using Enhanced ROM Compression Technique

A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations

FPGA-Based True Random Number Generation Using Programmable Delays in Oscillator-Rings

Design of a Common High-Performance Data Acquisition System for Physics Experiments at HIAF

A General Framework for FPGA-Based Real-Time Emulation of Electrical Machines for HIL Applications

Efficient Time-to-Digital Converters in 20 nm FPGAs With Wave Union Methods

FPGA-based fast image warping with data-parallelization schemes

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