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CMOS Clock-Gated Synchronous Up/Down Counter With High-Speed Local Clock Generation and Compact Toggle Flip-Flop

IEEE transactions on circuits and systems. I, Regular papers, 2023-12, Vol.70 (12), p.5316-5327

2023

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Low-Power High-Speed Sense-Amplifier-Based Flip-Flops With Conditional Bridging

IEEE access, 2023, Vol.11, p.121835-121844

2023

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CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction

IEEE transactions on circuits and systems. II, Express briefs, 2009-01, Vol.56 (1), p.11-15

2009

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Conditional-capture flip-flop for statistical power reduction

IEEE journal of solid-state circuits, 2001-08, Vol.36 (8), p.1263-1271

2001

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Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation

IEEE transactions on circuits and systems. II, Express briefs, 2009-08, Vol.56 (8), p.649-653

2009

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A DFE Receiver With Equalized VREF for Multidrop Single-Ended Signaling

IEEE transactions on circuits and systems. II, Express briefs, 2013-07, Vol.60 (7), p.412-416

2013

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CMOS Charge Pump With No Reversion Loss and Enhanced Drivability

IEEE transactions on very large scale integration (VLSI) systems, 2014-06, Vol.22 (6), p.1441-1445

2014

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Presetting pulse-based flip-flop

2008 IEEE International Symposium on Circuits and Systems, 2008, p.588-591

2008

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A Single-Phase Contention-and Redundant Transition-Free Flip-Flop With Improved DQ Latency

IEEE journal of solid-state circuits, 2024-10, p.1-12

2024

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PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion

2008 IEEE International Symposium on Circuits and Systems, 2008, p.1902-1905

2008

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Charge recycling differential logic (CRDL) for low power application

IEEE journal of solid-state circuits, 1996-09, Vol.31 (9), p.1267-1276

1996

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CMOS Differential Logic Family With Conditional Operation for Low-Power Application

IEEE transactions on circuits and systems. II, Express briefs, 2008-05, Vol.55 (5), p.437-441

2008

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CMOS charge pump with separated charge sharing for improved boosting ratio and relaxed timing restriction

2011 9th IEEE International Conference on ASIC, 2011, p.133-136

2011

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Conditional-capture flip-flop technique for statistical power reduction

2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056), 2000, p.290-291

2000

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An efficient dual-supply design for low-power mobile systems

2012 International SoC Design Conference (ISOCC), 2012, p.359-362

2012

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Charge recycling differential logic for low-power application

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC, 1996, Vol.39, p.302-303

1996

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Novel explicit pulse-based flip-flop for high speed and low power SoCs

IEICE Electronics Express, 2007-01, Vol.4 (23), p.731-737

2007

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A high current driving charge pump with current regulation method

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005, 2005, p.207-210

2005

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ASMD with duty cycle correction scheme for high-speed DRAM

Electronics letters, 2001-08, Vol.37 (16), p.1-1

2001

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Nonoverlapping Cuspid-Pulsed Flip-Flop

2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007, p.158-161

2007

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Variable sampling window flip-flop for low-power application

2003 IEEE International Symposium on Circuits and Systems (ISCAS), 2003, Vol.5, p.V-V

2003

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Data-dependent evaluating latched CMOS differential logic family for statistical power reduction

2000 IEEE International Symposium on Circuits and Systems (ISCAS), 2000, Vol.1, p.760-763 vol.1

2000

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A true single-phase clocking scheme for low-power and high-speed VLSI

1997 IEEE International Symposium on Circuits and Systems (ISCAS), 1997, Vol.3, p.1904-1907 vol.3

1997

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CMOS Clock-Gated Synchronous Up/Down Counter With High-Speed Local Clock Generation and Compact Toggle Flip-Flop

Low-Power High-Speed Sense-Amplifier-Based Flip-Flops With Conditional Bridging

CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction

Conditional-capture flip-flop for statistical power reduction

Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation

A DFE Receiver With Equalized VREF for Multidrop Single-Ended Signaling

CMOS Charge Pump With No Reversion Loss and Enhanced Drivability

Presetting pulse-based flip-flop

A Single-Phase Contention-and Redundant Transition-Free Flip-Flop With Improved DQ Latency

PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion

Charge recycling differential logic (CRDL) for low power application

CMOS Differential Logic Family With Conditional Operation for Low-Power Application

CMOS charge pump with separated charge sharing for improved boosting ratio and relaxed timing restriction

Conditional-capture flip-flop technique for statistical power reduction

An efficient dual-supply design for low-power mobile systems

Charge recycling differential logic for low-power application

Novel explicit pulse-based flip-flop for high speed and low power SoCs

A high current driving charge pump with current regulation method

ASMD with duty cycle correction scheme for high-speed DRAM

Nonoverlapping Cuspid-Pulsed Flip-Flop

Variable sampling window flip-flop for low-power application

Data-dependent evaluating latched CMOS differential logic family for statistical power reduction

A true single-phase clocking scheme for low-power and high-speed VLSI

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