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Fast detection of data retention faults and other SRAM cell open defects

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-01, Vol.25 (1), p.167-180

2006

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Scan-based BIST fault diagnosis

IEEE transactions on computer-aided design of integrated circuits and systems, 1999-02, Vol.18 (2), p.203-211

1999

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Diagnosis of scan chain failures

Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223), 1998, p.217-222

Yuejian Wu

1998

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Designs for reducing test time of distributed small embedded SRAMs

19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings, 2004, p.120-128

2004

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Single-reference multiple intermediate signature (SREMIS) analysis for BIST

IEEE transactions on computers, 1995-06, Vol.44 (6), p.817-825, Article 817

1995

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BIST fault diagnosis in scan-based VLSI environments

Proceedings International Test Conference 1996. Test and Design Validity, 1996, p.48-57

1996

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Accelerated path delay fault simulation

Digest of Papers. 1992 IEEE VLSI Test Symposium, 1992, p.1-6

1992

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On fault coverage in VLSI built-in self-test with multiple intermediate signature analysis

Proceedings of Canadian Conference on Electrical and Computer Engineering, 1993, p.449-452 vol.1

1993

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A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs

Design, Automation and Test in Europe, 2005, p.852-857

2005

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Reducing hardware with fuzzy multiple signature analysis

IEEE design & test of computers, 1995, Vol.12 (1), p.68-74

1995

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Minimal hardware multiple signature analysis for BIST

Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium, 1993, p.17-20

1993

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A fuzzy multiple signature compaction scheme for BIST

Proceedings First Asian Test Symposium (ATS `92), 1992, p.247-252

1992

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Fast detection of data retention faults and other SRAM cell open defects

Scan-based BIST fault diagnosis

Diagnosis of scan chain failures

Designs for reducing test time of distributed small embedded SRAMs

Single-reference multiple intermediate signature (SREMIS) analysis for BIST

BIST fault diagnosis in scan-based VLSI environments

Accelerated path delay fault simulation

On fault coverage in VLSI built-in self-test with multiple intermediate signature analysis

A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs

Reducing hardware with fuzzy multiple signature analysis

Minimal hardware multiple signature analysis for BIST

A fuzzy multiple signature compaction scheme for BIST

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