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CSyn-fp: Standard Cell Synthesis of Advanced Nodes With Simultaneous Transistor Folding and Placement

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-02, Vol.43 (2), p.1-1

2024

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Deeper Weight Pruning Without Accuracy Loss in Deep Neural Networks: Signed-Digit Representation-Based Approach

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-03, Vol.41 (3), p.656-668

2022

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Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-12, Vol.35 (12), p.2068-2081

2016

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Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs

Integration (Amsterdam), 2014-03, Vol.47 (2), p.184-194

2014

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An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-03, Vol.32 (3), p.392-405

2013

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ECO routing based on network flow method

Integration (Amsterdam), 2022-09, Vol.86, p.1-8

2022

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Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-01, Vol.30 (1), p.96-109

2011

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Scheduling and Resource Binding Algorithm Considering Timing Variation

IEEE transactions on very large scale integration (VLSI) systems, 2011-02, Vol.19 (2), p.205-216

2011

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Edge layer embedding algorithm for mitigating on-package variation in 3D clock tree synthesis

Integration (Amsterdam), 2014, Vol.47 (4), p.476-486

2014

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Common Kernels and Convolutions in Binary- and Ternary-Weight Neural Networks

Journal of circuits, systems, and computers, 2021-07, Vol.30 (9), p.2150158

2021

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Eliminating Minimum Implant Area Violations With Design Quality Preservation

IEEE transactions on very large scale integration (VLSI) systems, 2023-05, Vol.31 (5), p.1-11

2023

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Simultaneous Transistor Folding and Placement in Standard Cell Layout Synthesis

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021, p.1-8

2021

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Optimal voltage allocation techniques for dynamically variable voltage processors

ACM transactions on embedded computing systems, 2005-02, Vol.4 (1), p.211-230

2005

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Post-silicon tuning aware wafer matching algorithm for 3d integration of ICs

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), 2014, p.511-514

2014

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Synthesis and exploration of clock spines

Chronic diseases and translational medicine, 2018-09, Vol.12 (5), p.241-248

2018

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Context-driven hybrid image inpainting

IET image processing, 2015-10, Vol.9 (10), p.866-873

2015

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Deeper Weight Pruning without Accuracy Loss in Deep Neural Networks

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, p.73-78

2020

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Machine Learning Driven Synthesis of Clock Gating

2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2023, p.1-6

2023

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Loosely coupled multi-bit flip-flop allocation for power reduction

Integration (Amsterdam), 2017-06, Vol.58, p.125-133

2017

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High-level synthesis for low power based on network flow method

IEEE transactions on very large scale integration (VLSI) systems, 2003-06, Vol.11 (3), p.364-375

2003

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Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement

2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021, p.232-235

2021

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An optimal allocation of carry-save-adders in arithmetic circuits

IEEE transactions on computers, 2001-03, Vol.50 (3), p.215-233

2001

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Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes

Integration (Amsterdam), 2016-01, Vol.52, p.91-101

2016

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Synthesis of arithmetic circuits considering layout effects

IEEE transactions on computer-aided design of integrated circuits and systems, 2003-11, Vol.22 (11), p.1487-1503

2003

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Clock Tree synthesis for TSV-based 3D IC designs

ACM transactions on design automation of electronic systems, 2011-10, Vol.16 (4), p.1-21

2011

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CSyn-fp: Standard Cell Synthesis of Advanced Nodes With Simultaneous Transistor Folding and Placement

Deeper Weight Pruning Without Accuracy Loss in Deep Neural Networks: Signed-Digit Representation-Based Approach

Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling

Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs

An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs

ECO routing based on network flow method

Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization

Scheduling and Resource Binding Algorithm Considering Timing Variation

Edge layer embedding algorithm for mitigating on-package variation in 3D clock tree synthesis

Common Kernels and Convolutions in Binary- and Ternary-Weight Neural Networks

Eliminating Minimum Implant Area Violations With Design Quality Preservation

Simultaneous Transistor Folding and Placement in Standard Cell Layout Synthesis

Optimal voltage allocation techniques for dynamically variable voltage processors

Post-silicon tuning aware wafer matching algorithm for 3d integration of ICs

Synthesis and exploration of clock spines

Context-driven hybrid image inpainting

Deeper Weight Pruning without Accuracy Loss in Deep Neural Networks

Machine Learning Driven Synthesis of Clock Gating

Loosely coupled multi-bit flip-flop allocation for power reduction

High-level synthesis for low power based on network flow method

Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement

An optimal allocation of carry-save-adders in arithmetic circuits

Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes

Synthesis of arithmetic circuits considering layout effects

Clock Tree synthesis for TSV-based 3D IC designs

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