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Design Insights of Nanosheet FET and CMOS Circuit Applications at 5-nm Technology Node
IEEE transactions on electron devices, 2022-08, Vol.69 (8), p.4115-4122
2022
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Design insights into RF/analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications
International journal of RF and microwave computer-aided engineering, 2021-12, Vol.31 (12), p.n/a
2021
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Performance Enhancement of FinFET Devices with Gate-Stack (GS) High-K Dielectrics for Nanoscale Applications
SILICON, 2018-11, Vol.10 (6), p.2419-2429
2018
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Design and Temperature Assessment of Junctionless Nanosheet FET for Nanoscale Applications
SILICON, 2022-06, Vol.14 (8), p.3823-3834
2022
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A Comprehensive Analysis of Junctionless Tri-Gate (TG) FinFET Towards Low-Power and High-Frequency Applications at 5-nm Gate Length
SILICON, 2022-04, Vol.14 (5), p.2009-2021
2022
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Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes
International journal of electronics and communications, 2022-02, Vol.145, p.154069, Article 154069
2022
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Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length
International journal of electronics and communications, 2021-07, Vol.137, p.153803, Article 153803
2021
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Junctionless Gate-all-around Nanowire FET with Asymmetric Spacer for Continued Scaling
SILICON, 2022-08, Vol.14 (13), p.7461-7471
2022
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Circuit Analysis and Optimization of GAA Nanowire FET Towards Low Power and High Switching
SILICON, 2022-11, Vol.14 (16), p.10401-10411
2022
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Surface Potential Modeling of Graded-Channel Gate-Stack (GCGS) High-K Dielectric Dual-Material Double-Gate (DMDG) MOSFET and Analog/RF Performance Study
SILICON, 2018-11, Vol.10 (6), p.2865-2875
2018
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Beyond Moore's law – A critical review of advancements in negative capacitance field effect transistors: A revolution in next-generation electronics
Materials science in semiconductor processing, 2024-04, Vol.173, p.108116, Article 108116
2024
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Design Space Optimization for Eradication of NDR Effect in Dielectric/Ferroelectric Stacked Negative Capacitance Multi-Gate FETs at Sub-3nm Technology for Digital/Analog/RF Applications
IEEE transactions on dielectrics and electrical insulation, 2024-07, p.1-1
2024
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Pushing the Boundaries: Design and Simulation Approach of Negative Capacitance Nanosheet FETs with Ferroelectric and Dielectric Spacers at the Sub‑3 nm Technology Node for Analog/RF/Mixed Signal Applications
ACS applied electronic materials, 2024-05, Vol.6 (5), p.3206-3215
2024
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A Proposal for Optimization of Spacer Engineering at Sub-5-nm Technology Node for JL-TreeFET: A Device to Circuit Level Implementation
IEEE transactions on electron devices, 2024-01, Vol.71 (1), p.453-460
2024
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A novel bottom-spacer ground-plane (BSGP) FinFET for improved logic and analog/RF performance
International journal of electronics and communications, 2020-12, Vol.127, p.153459, Article 153459
2020
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A two-dimensional (2D) analytical surface potential and subthreshold current model for the underlap dual-material double-gate (DMDG) FinFET
Journal of computational electronics, 2016-12, Vol.15 (4), p.1316-1325
2016
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A Two-Dimensional (2D) Analytical Modeling and Improved Short Channel Performance of Graded-Channel Gate-Stack (GCGS) Dual-Material Double-Gate (DMDG) MOSFET
SILICON, 2018-11, Vol.10 (6), p.2399-2407
2018
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Investigation of Short Channel Effects (SCEs) and Analog/RF Figure of Merits (FOMs) of Dual-Material Bottom-Spacer Ground-Plane (DMBSGP) FinFET
SILICON, 2020-10, Vol.12 (10), p.2283-2291
2020
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A novel design of coplanar 8-bit ripple carry adder using field-coupled quantum-dot cellular automata nanotechnology
European physical journal plus, 2023-08, Vol.138 (8), p.731, Article 731
2023
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First Principle Study of Doped Graphene for FET Applications
SILICON, 2019-02, Vol.11 (1), p.277-286
2019
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A two-dimensional (2D) analytical surface potential and subthreshold current model for underlap dual-material double-gate (DMDG) FinFET
Journal of computational electronics, 2016-08
2016
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Suppression of Short Channel Effects(SCEs) by Dual Material Gate Vertical Surrounding Gate(DMGVSG) MOSFET: 3-D TCAD Simulation
Procedia engineering, 2013, Vol.64, p.125-132
2013
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