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A Distributed Rate-Control Approach to Reduce Communication Burdens in VSNs

IEEE access, 2023, Vol.11, p.1011-1022

2023

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A Study on the Impact of Multiview Distributed Feature Coding on a Multicamera Vehicle Tracking System at Roundabouts

IEEE access, 2022, Vol.10, p.39502-39517

2022

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The Medaka Inbred Kiyosu-Karlsruhe (MIKK) panel

Genome Biology, 2022-02, Vol.23 (1), p.59-32, Article 59

2022

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Real Time LP Decoding of LDPC Codes for High Correction Performance Applications

IEEE wireless communications letters, 2016-12, Vol.5 (6), p.676-679

2016

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Power Consumption Models for Decimation FIR Filters in Multistandard Receivers

VLSI Design, 2012-01, Vol.2012 (2012), p.419-433

2012

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Fast Converging ADMM-Penalized Algorithm for LDPC Decoding

IEEE communications letters, 2016-04, Vol.20 (4), p.648-651

2016

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Multicore and Manycore Implementations of ADMM-based Decoders for LDPC Decoding

Journal of signal processing systems, 2018-11, Vol.90 (11), p.1551-1567

2018

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Hardware design of Euclidean Projection modules for ADMM LDPC decoding

2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2018, p.73-76

2018

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Design of a reconfigurable digital decimation filter for flexible GNSS receivers

2016 5th International Conference on Multimedia Computing and Systems (ICMCS), 2016, p.230-235

2016

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Comparison of different schedulings for the ADMM based LDPC decoding

2016 9th International Symposium on Turbo Codes and Iterative Information Processing (ISTC), 2016, p.51-55

2016

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Implementation aspects of a pipeline ADMM-based LP decoding of LDPC convolutional codes

2018 IEEE Wireless Communications and Networking Conference (WCNC), 2018, p.1-6

2018

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ADMM hardware decoder for regular LDPC codes using a NISC-based architecture

2018 IEEE Wireless Communications and Networking Conference (WCNC), 2018, p.1-6

2018

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Multicore implementation of LDPC decoders based on ADMM algorithm

2016 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2016, p.971-975

2016

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Deep Multi-modal Object Detection for Autonomous Driving

2021 18th International Multi-Conference on Systems, Signals & Devices (SSD), 2021, p.7-11

2021

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Feature-based Vehicle Tracking at Roundabouts in Visual Sensor Networks

2020 17th International Multi-Conference on Systems, Signals & Devices (SSD), 2020, p.167-172

2020

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High Level Design Flow Targeting Real Multistandard Circuit Designer Requirements

Journal of communication and computer, 2011-05, Vol.8 (5), p.335-346

2011

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Design and Implementation of a Reconfigurable Decimation and Channel Selection Filter for GSM and UMTS Radio Standards

2009 IEEE Wireless Communications and Networking Conference, 2009, p.1-6

2009

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Low complexity ADMM-LP based decoding strategy for LDPC convolutional codes

2017 25th International Conference on Software, Telecommunications and Computer Networks (SoftCOM), 2017, p.1-5

2017

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Hardware complexity reduction of LDPC-CC decoders based on message-passing approaches

2016 17th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA), 2016, p.679-684

2016

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Experiments on designing low power decimation filter for multistandard receiver on heterogeneous targets

2009 17th European Signal Processing Conference, 2009, p.1284-1288

2009

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Power consumption estimation models for FIR decimation filters in multi-standard receivers

2011 IEEE GCC Conference and Exhibition (GCC), 2011, p.617-620

2011

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Low Power Implementation of Digital Filters using DBNS Representation and Sub-expression Sharing

2008 2nd International Conference on Signals, Circuits and Systems, 2008, p.1-6

2008

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Evaluation of FIR filters implementations for low power multistandard receivers

5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2010, p.1-5

2010

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Low Power Implementation of Decimation Filters in Multistandard Radio Receiver Using Optimized Multiplication-Accumulation Unit

2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007, p.1183-1186

2007

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Low power FPGA-based implementation of decimating filters for multistandard receiver

International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006, 2006, p.10-14

2006

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Energy Consumption
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Iterative Decoding
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A Distributed Rate-Control Approach to Reduce Communication Burdens in VSNs

A Study on the Impact of Multiview Distributed Feature Coding on a Multicamera Vehicle Tracking System at Roundabouts

The Medaka Inbred Kiyosu-Karlsruhe (MIKK) panel

Real Time LP Decoding of LDPC Codes for High Correction Performance Applications

Power Consumption Models for Decimation FIR Filters in Multistandard Receivers

Fast Converging ADMM-Penalized Algorithm for LDPC Decoding

Multicore and Manycore Implementations of ADMM-based Decoders for LDPC Decoding

Hardware design of Euclidean Projection modules for ADMM LDPC decoding

Design of a reconfigurable digital decimation filter for flexible GNSS receivers

Comparison of different schedulings for the ADMM based LDPC decoding

Implementation aspects of a pipeline ADMM-based LP decoding of LDPC convolutional codes

ADMM hardware decoder for regular LDPC codes using a NISC-based architecture

Multicore implementation of LDPC decoders based on ADMM algorithm

Deep Multi-modal Object Detection for Autonomous Driving

Feature-based Vehicle Tracking at Roundabouts in Visual Sensor Networks

High Level Design Flow Targeting Real Multistandard Circuit Designer Requirements

Design and Implementation of a Reconfigurable Decimation and Channel Selection Filter for GSM and UMTS Radio Standards

Low complexity ADMM-LP based decoding strategy for LDPC convolutional codes

Hardware complexity reduction of LDPC-CC decoders based on message-passing approaches

Experiments on designing low power decimation filter for multistandard receiver on heterogeneous targets

Power consumption estimation models for FIR decimation filters in multi-standard receivers

Low Power Implementation of Digital Filters using DBNS Representation and Sub-expression Sharing

Evaluation of FIR filters implementations for low power multistandard receivers

Low Power Implementation of Decimation Filters in Multistandard Radio Receiver Using Optimized Multiplication-Accumulation Unit

Low power FPGA-based implementation of decimating filters for multistandard receiver

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