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Implementation of fully isolated Low Vgs nLDMOS with low specific on-resistance

2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs, 2011, p.24-27

2011

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Logic Programming in a Fragment of Intuitionistic Temporal Linear Logic

Lecture notes in computer science, 2001, p.315-330

2001

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Low Vgs P-ch LDMOS with Sallow Pwell from 8V to 60V

2010 22nd International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2010, p.177-180

2010

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A new 8V - 60V rated low Vgs NLDMOS structure with enhanced specific on-resistance

2010 22nd International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2010, p.245-248

2010

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A 28GHz CMOS direct conversion transceiver with packaged antenna arrays for 5G cellular system

2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2017, p.69-72

2017

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A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.278-613

2008

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Emission of polybrominated diphenyl ethers (PBDEs) in use of electric/electronic equipment and recycling of e-waste in Korea

Science of the total environment, 2014, Vol.470-71, p.1414-1421

2014

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A Two-Level On-Chip Bus System Based on Multiplexers

Advances in Computer Systems Architecture, 2004, p.363-372

2004

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Optimization of control gate material and structure for enhancing 20nm 64Gb NAND flash reliability

Proceedings of Technical Program of 2012 VLSI Technology, System and Application, 2012, p.1-2

2012

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The effects of Ag, Cu compositions and Zn doping on the electromigration performance of Pb-free solders

2009 59th Electronic Components and Technology Conference, 2009, p.922-929

2009

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Minor alloying effects of Ni or Zn on microstructure and microhardness of Pb-free solders

2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 2011, p.84-89

2011

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Controlling the interfacial reactions in Pb-free interconnections by adding minor alloying elements to Sn-rich solders

2008 58th Electronic Components and Technology Conference, 2008, p.478-484

2008

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Development of Welding Profile Sensor and Its Application

2008 International Conference on Smart Manufacturing Application, 2008, p.24-29

2008

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IP forwarding engine with VC merging in ATM-based MPLS system

Proceedings Ninth International Conference on Computer Communications and Networks (Cat.No.00EX440), 2000, p.459-462

2000

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High speed optical transmission R&D in ETRI

Digest of the 9th International Conference on Optical Internet (COIN 2010), 2010, p.1-4

2010

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Integration of Low Resistive CVD-W Interconnects for sub-50nm FEOL application

2008 International Interconnect Technology Conference, 2008, p.147-149

2008

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A 5.0Gbps/pin packet-based DRAM with low latency receiver and process insensitive PLL

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005, 2005, p.50-51

2005

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On-board optical interconnection of 2.5Gb/s x 12 channels data using fiber-embedded PCB

The 6th International Conference on Advanced Communication Technology, 2004, 2004, Vol.1, p.286-290

2004

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Wavelength tunable optical pulse generation at various repetition rates from a semiconductor fiber ring laser

LEOS 2001. 14th Annual Meeting of the IEEE Lasers and Electro-Optics Society (Cat. No.01CH37242), 2001, Vol.2, p.717-718 vol.2

2001

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Demonstration of 2.5Gb/s optical interconnection using 45°-ended connection blocks in fiber- and waveguide-embedded PCBs

Proceedings - Electronic Components Conference, 2004

2004

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Demonstration of 2.5Gb/s optical interconnection using 45/spl deg/-ended connection blocks in fiber- and waveguide-embedded PCBs

2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546), 2004, Vol.2, p.1547-1551 Vol.2

2004

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A 512Mbit, 3.2Gbps/pin packet-based DRAM with cost-efficient clock generation and distribution scheme

2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525), 2004, p.36-37

2004

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A 512Mbit, 3.2Gbps/pin packet-based DRAM with cost-efficient clock generation and distribution scheme

2003

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Implementation of fully isolated Low Vgs nLDMOS with low specific on-resistance

Logic Programming in a Fragment of Intuitionistic Temporal Linear Logic

Low Vgs P-ch LDMOS with Sallow Pwell from 8V to 60V

A new 8V - 60V rated low Vgs NLDMOS structure with enhanced specific on-resistance

A 28GHz CMOS direct conversion transceiver with packaged antenna arrays for 5G cellular system

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

Emission of polybrominated diphenyl ethers (PBDEs) in use of electric/electronic equipment and recycling of e-waste in Korea

A Two-Level On-Chip Bus System Based on Multiplexers

Optimization of control gate material and structure for enhancing 20nm 64Gb NAND flash reliability

The effects of Ag, Cu compositions and Zn doping on the electromigration performance of Pb-free solders

Minor alloying effects of Ni or Zn on microstructure and microhardness of Pb-free solders

Controlling the interfacial reactions in Pb-free interconnections by adding minor alloying elements to Sn-rich solders

Development of Welding Profile Sensor and Its Application

IP forwarding engine with VC merging in ATM-based MPLS system

High speed optical transmission R&D in ETRI

Integration of Low Resistive CVD-W Interconnects for sub-50nm FEOL application

A 5.0Gbps/pin packet-based DRAM with low latency receiver and process insensitive PLL

On-board optical interconnection of 2.5Gb/s x 12 channels data using fiber-embedded PCB

Wavelength tunable optical pulse generation at various repetition rates from a semiconductor fiber ring laser

Demonstration of 2.5Gb/s optical interconnection using 45°-ended connection blocks in fiber- and waveguide-embedded PCBs

Demonstration of 2.5Gb/s optical interconnection using 45/spl deg/-ended connection blocks in fiber- and waveguide-embedded PCBs

A 512Mbit, 3.2Gbps/pin packet-based DRAM with cost-efficient clock generation and distribution scheme

A 512Mbit, 3.2Gbps/pin packet-based DRAM with cost-efficient clock generation and distribution scheme

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