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Quality Evaluation Method for Chest X-Ray Images using the Reference Patterns

2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022, p.266-269

2022

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A Neural Text-to-Speech Model Utilizing Broadcast Data Mixed with Background Music

ICASSP 2021 - 2021 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2021, p.6603-6607

2021

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A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.446-448

2022

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Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, p.1-6

2015

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Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices

2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2017, p.61-72

2017

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Highly reliable vertical NAND technology with biconcave shaped storage layer and leakage controllable offset structure

2010 Symposium on VLSI Technology, 2010, p.173-174

2010

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A highly manufacturable integration technology of 20nm generation 64Gb multi-level NAND flash memory

2011 Symposium on VLSI Technology - Digest of Technical Papers, 2011, p.70-71

2011

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Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50nm DRAM Technology

2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers, 2006, p.32-33

2006

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Optimization of control gate material and structure for enhancing 20nm 64Gb NAND flash reliability

Proceedings of Technical Program of 2012 VLSI Technology, System and Application, 2012, p.1-2

2012

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Implementation of fully isolated Low Vgs nLDMOS with low specific on-resistance

2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs, 2011, p.24-27

2011

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7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate

2015 IEEE International Solid State Circuits Conference (ISSCC), 2015, p.1-3

2015

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A Novel Simulation Methodology Reflecting System Power Scenario using a Markov-Chain-based Stochastic Random Power Model

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), 2022, p.929-936

2022

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Gate-first high-k/metal gate DRAM technology for low power and high performance products

2015 IEEE International Electron Devices Meeting (IEDM), 2015, p.26.6.1-26.6.4

2015

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Implementation of PHY module for personal and portable Cognitive Radio devices

2011 IEEE International Conference on Consumer Electronics (ICCE), 2011, p.451-452

2011

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PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion

2008 IEEE International Symposium on Circuits and Systems, 2008, p.1902-1905

2008

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Inherent Issues and Challenges of Program Disturbance of 3D NAND Flash Cell

2012 4th IEEE International Memory Workshop, 2012, p.1-4

2012

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Non thermal microplasma jet array for wound healing

2012 Abstracts IEEE International Conference on Plasma Science, 2012, p.2E-4-2E-4

2012

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Sural Artery Flap, Distally or Proximally Based

Journal of Reconstructive Microsurgery, 2006, Vol.22 (4)

2006

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Reversed Arterial and Venous Flow in Free-Flap Surgery for Leg Reconstruction

Journal of Reconstructive Microsurgery, 2006, Vol.22 (4)

2006

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Development of Digital Signage Modules composed of Mini-LEDs using Laser-Assisted Bonding (LAB) Technology

2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 2020, p.1031-1036

2020

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Low Voltage and High Speed 1Xnm 1T1C FE-RAM with Ultra-Thin 5nm HZO

2021 IEEE International Electron Devices Meeting (IEDM), 2021, p.33.3.1-33.3.4

2021

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A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.278-613

2008

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Adaptive Resource Allocation for OFDMA with Mixed Frame Structure

VTC Spring 2009 - IEEE 69th Vehicular Technology Conference, 2009, p.1-5

2009

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Magnetic Refrigeration Properties of La0.8Ca0.2Mn0.9957Fe0.01O3

IEEE transactions on magnetics, 2009, Vol.45 (6), p.2565-2568

2009

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Modeling and optimization of the chip level program disturbance of 3D NAND Flash memory

2013 5th IEEE International Memory Workshop, 2013, p.147-150

2013

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Quality Evaluation Method for Chest X-Ray Images using the Reference Patterns

A Neural Text-to-Speech Model Utilizing Broadcast Data Mixed with Background Music

A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus

Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM

Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices

Highly reliable vertical NAND technology with biconcave shaped storage layer and leakage controllable offset structure

A highly manufacturable integration technology of 20nm generation 64Gb multi-level NAND flash memory

Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50nm DRAM Technology

Optimization of control gate material and structure for enhancing 20nm 64Gb NAND flash reliability

Implementation of fully isolated Low Vgs nLDMOS with low specific on-resistance

7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate

A Novel Simulation Methodology Reflecting System Power Scenario using a Markov-Chain-based Stochastic Random Power Model

Gate-first high-k/metal gate DRAM technology for low power and high performance products

Implementation of PHY module for personal and portable Cognitive Radio devices

PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion

Inherent Issues and Challenges of Program Disturbance of 3D NAND Flash Cell

Non thermal microplasma jet array for wound healing

Sural Artery Flap, Distally or Proximally Based

Reversed Arterial and Venous Flow in Free-Flap Surgery for Leg Reconstruction

Development of Digital Signage Modules composed of Mini-LEDs using Laser-Assisted Bonding (LAB) Technology

Low Voltage and High Speed 1Xnm 1T1C FE-RAM with Ultra-Thin 5nm HZO

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

Adaptive Resource Allocation for OFDMA with Mixed Frame Structure

Magnetic Refrigeration Properties of La0.8Ca0.2Mn0.9957Fe0.01O3

Modeling and optimization of the chip level program disturbance of 3D NAND Flash memory

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